Browsing by Author "Hua, Chung-Hsien"

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A noise-tolerant matchline scheme with XOR-based conditional keeper for energy-efficient TCAM
(2006)
Hua, Chung-Hsien
;
Peng, Chi-Wei
;
Hwang, Wei
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A novel AND-type match-line scheme with XOR-based conditional keeper for ternary content-addressable memory (TCAM) are presented in this paper. The XOR-based conditional keeper is turned off at some critical moments to reduce the search time and power consumption. High fan-in AND-type match-line schemes are used to demonstrate the effectiveness of the XOR-based conditional keeper in the presence of noise sources. 37.8% search time reduction and 15.6% power saving are achieved by using the proposed TCAM architecture. Based on TSMC 0.13 mu m CMOS technology at 1.2V supply voltage, a 256 words x 128 bits ternary CAM is designed. The simulation results show that the search time of proposed TCAM architecture is 1.17ns and energy metric of proposed TCAM architecture is 0.7520/search.
Power gating structure having data retention and intermediate modes
(2006-06-08)
Hua, Chung-Hsien
;
Hwang, Wei
The present invention provides a power gating structure having data retention and intermediate modes and able to operate under multiple modes. A conventional power gating structure has only turn-on and turn-off functions, and is used to suppress a leakage current problem which has become more and more serious in advance manufacture processes, under a turn-off mode. However, in a memory circuit, such as latch, register and SRAM, when the power gate is turned off, a new power gating structure is required for data retention. The power gating structure of the present invention can be set into one of 4 different operational modes: a data retention mode for maintaining the static noise margin of the memory, an intermediate mode for reducing the interference on ground and power levels, an active mode used when the circuit operates in normal condition, and a standby mode used when the circuit does not operate.
XOR-based conditional keeper and an architecture implementing its application to match lines
(2007-05-10)
Hua, Chung-Hsien
;
Peng, Chi-Wei
;
Hwang, Wei
The present invention discloses an XOR-based conditional keeper and an architecture implementing its application to match lines, wherein the XOR gate in the conditional keeper receives a clock signal synchronous with CAM (Content Addressable Memory) cells and cooperates with a floating signal from the floating node to create an XOR control signal, and the XOR control signal is transmitted to a P-type transistor to create a data signal to control the XOR-based conditional keeper so that the XOR-based conditional keeper can execute an appropriate corresponding action, which can replace the conventional keepers of merely “on” and “off” modes. Further, the XOR-based conditional keeper of the present invention can apply to the dynamic CAM match line architecture so that the dynamic match line can have lower power consumption, higher noise immunity, and high processing speed. Further, the XOR-based conditional keeper of the present invention can also apply to all kinds of dynamic circuits, particularly to a high fan-in circuit.