Browsing by Author "Huang, Chen-Chih"

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99.4% Peak Audio Signal Recovery Rate and Ultra-Low 0.32dB Matching Error with 10Hz High Resolution Filter Fitting Wearable Aided Speech Compensation System
(2015)
Lin, Yen-Ting
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Lai, Shin-Chi
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Chen, Shin-Hao
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Peng, Shen-Yu
;
Chen, Ke-Horng
to get high sound quality, the proposed adaptive speech compensation (ASC) system fits psychoacoustic curves for individual needs. Moreover, characteristics of the speakers are considered by real-time speaker impedance estimation (RT-SIE) technique. Hence, original signal can be restored for every user with any speakers. ASC system has 99.4% peak original signal recovery rate by predicting and controlling output signal precisely. And the built-in 10Hz high resolution acoustic filter fitting scheme (AFFS) has less than 0.32dB matching error with an over 80dB hearing loss.
A 2.5W Tablet Speaker Delivering 3.2W Pseudo High Power by Psychoacoustic Model Based Adaptive Power Management System
(2014)
Chen, Shin-Hao
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Peng, Shen-Yu
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Chen, Ke-Horng
;
Lai, Shin-Chi
;
Kang, Sheng
for a 2.5W speaker in tablets, the proposed adaptive power management (APM) system can deliver a pseudo high power of 3.2W with a +/- 4V supply because it suppresses 0.7W power on tones that may damage a 2.5W speaker and escape the notice of human ears. With z-domain digital signal processing (z-DSP) and psychoacoustic model, high efficient power management and high sound quality can be achieved simultaneously. Conventional automatic gain control (AGC) only has the ability of 0.32W power suppression. Moreover, suppressing power by conventional clipping technique increases total-harmonic-distortion (THD). In contrast, the proposed real-time dynamic loading impedance (RT-DLI) monitoring brings forward a way to solve the problem on speaker damage while keeping low THD during high sound pressure level (SPL). THD in the APM system is slightly higher than that of original sound 1.1dB, comparing to the disadvantage of 8.6dB increasing caused by conventional clipping technique.
A Battery-Free 217 nW Static Control Power Buck Converter for Wireless RF Energy Harvesting With alpha-Calibrated Dynamic On/Off Time and Adaptive Phase Lead Control
(2012-04-01)
Huang, Tzu-Chi
;
Hsieh, Chun-Yu
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Yang, Yao-Yi
;
Lee, Yu-Huei
;
Kang, Yu-Chai
Abattery-free nano-power buck converter with a proposed dynamic on/off time (DOOT) control can achieve high conversion efficiency over a wide load range. The DOOT control can predict the on/off time at different input voltages without a power consuming zero current detection (ZCD) circuit, as well as suppress static power in idle periods. To adapt to the fluctuations in a harvesting system, the proposed alpha-calibration scheme guarantees accurate ZCD over process, voltage variation, and temperature (PVT) in the DOOT to improve power conversion efficiency. Furthermore, the adaptive phase lead (APL) mechanism can improve inherent propagation delay attributable to low-power and non-ideal comparator, thus improving load regulation by a maximum of 30 mV. The test chip was implemented in 0.25-mu m CMOS process with a die area of 0.39 mm(2). Experimental results showed 95% peak efficiency, low static power of 217 nW and good load regulation of 0.1 mV/mA, which are suitable for RF energy harvesting applications.
A Dual-Level Dual-Phase Pulse-Width Modulation Class-D Amplifier with 0.001% THD, 112 dB SNR
(2014-01-01)
Yang, Shang-Hsien
;
Yang, Yuan-Han
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Chen, Ke-Horng
;
Hung, Chung-Chih
;
Wey, Chin-Long
this paper presents a dual-level dual-phase pulse-width modulation (DLDP PWM) Class-D audio amplifier circuit which enhance amplifier linearity and reduce distortion. The proposed DLDP PWM Class-D audio amplifier includes two sets of non-overlapping triangular waves, each at its respectful offset levels. Each set of triangular waves is composed of two 180 degrees out-of-phase triangular waves. The differential power stage consists of 8 power transistors, with voltage swings up to +/- 6V. Simulated results shows that the proposed DLDP PWM Class-D audio amplifier features an SNR up to 105 dB, and the THD is suppressed below 0.001 %, with the 3rd harmonic below -102 dBV.
A DVS Embedded Power Management for High Efficiency Integrated SoC in UWB System
(2009)
Lee, Yu-Huei
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Wang, Shih-Jung
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Yang, Yao-Yi
;
Zheng, Kuo-Lin
;
Chen, Po-Fung
The proposed power management module with 1 V low-voltage PWM controller and dynamic self-biasing mechanism is designed to integrate with ultra-wide band (UWB) system. The on-chip pre-regulator with power conditioning circuit provides a constant and noiseless supply voltage. Instead of using large external compensation circuit, the compensation enhancement multistage amplifier increases system loop gain and stabilizes the system. Moreover, the proposed self-biasing mechanism enhances the power conversion efficiency by 4 % through the handover technique. The fabricated power management module occupies 0.356 mm(2) silicon in 65nm CMOS. With the excellent line/load transient response and the highest efficiency about 93.5%, the proposed power management has the qualification to be integrated in today's system-on-chip (SoC) applications.
A DVS Embedded Power Management for High Efficiency Integrated SoC in UWB System
(2010-11-01)
Lee, Yu-Huei
;
Yang, Yao-Yi
;
Chen, Ke-Horng
;
Lin, Ying-Hsi
;
Wang, Shih-Jung
The proposed power management module with a typical 1.2 V low-voltage PWM (LV-PWM) controller and dynamic voltage scaling (DVS) function is designed using 65 nm technology for integration with the ultra-wide band (UWB) system. The on-chip pre-regulator with a power conditioning circuit can provide a regulated supply voltage to the LV-controller. Moreover, the proposed handover technique can achieve the self-biasing mechanism to further reduce power dissipation. To operate in low voltage, the proposed compensation enhancement multistage amplifier (CEMA) can achieve high loop gain and ensure system stability without using any external compensation component. The fabricated power management module occupies 0.356 mm(2) silicon area with an excellent line/load transient response. Owing to the DVS function, the proposed power management can meet the power requirement in the UWB system and other RF transceiver systems.
A High Efficiency and Compact Size 65nm Power Management Module with 1.2V Low-Voltage PWM Controller for UWB System Application
(2009)
Lee, Yu-Huei
;
Wang, Shih-Jung
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Yang, Yao-Yi
;
Zheng, Kuo-Lin
;
Chen, Po-Fung
This 65 nm power management module with 1.2 V low-voltage PWM controller aims to integrate with ultra-wideband (UWB) system to get high efficiency and compact size. The on-chip pre-regulator with power conditioning circuit provides a constant and noiseless supply voltage. Thus, the voltage variation of battery has less effect on the low-voltage PWM controller. The proposed compensation enhancement multistage amplifier (CEMA) increases system loop gain and stabilizes the system without off-chip compensation circuit. With excellent line/load transient response, the proposed power management has the highest efficiency about 92% and 0.995 mm(2) silicon die area.
A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement
(2013-04-01)
Lee, Yu-Huei
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Peng, Shen-Yu
;
Chiu, Chao-Chang
;
Wu, Alex Chun-Hsien
;
Chen, Ke-Horng
A low quiescent current asynchronous digital-LDO (D-LDO) regulator integrated with a phase-locked loop (PLL)-modulated switching regulator (SWR) that achieves the near-optimum power management supply for core processor in system-on-chip (SoC). The parallel connection of the asynchronous D-LDO regulator and the ripple-based control SWR can accomplish fast-DVS (F-DVS) operation as well as high power conversion efficiency. The asynchronous D-LDO regulator controlled by bidirectional asynchronous wave pipeline realizes the F-DVS operation, which guarantees high million instructions per second (MIPS) performance of the core processor under distinct tasks. The use of a ripple-based control SWR operating with a leading phase amplifier ensures fast response and stable operation without the need for large equivalent-series-resistance, thus reducing the output voltage ripple for the enhancement of supply quality. The fabricated chip occupies 1.04 mm(2) in 40 nm CMOS technology. Experimental results show that a 94% peak efficiency with a voltage tracking speed of 7.5 V/mu s as well as the improved MIPS performance by 5.6 times was achieved.
A Low THD Clock-Free Class-D Audio Amplifier with an Increased Damping Resistor and Cross Offset Cancellation Technique
(2014-01-01)
Chou, Ying-Wei
;
Chien, Meng-Wei
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Chen, Shin-Chieh
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Chen, Ke-Horng
;
Lin, Ying-Hsi
an increased damping resistor (IDR) replaces high-order loop filter to simply reduce the total harmonic distortion (THD) of Class-D audio amplifier. Besides, cross offset cancellation (COC) technique minimizes the system offset voltage to avoid dc current flows to the speaker in the bridge tied load (BTL) structure. Furthermore, variable switching frequency characteristic in self-oscillating modulation spreads the electro-magnetic interference (EMI) impact out on the output frequency spectrum. Experimental results demonstrate that the proposed Class-D amplifier can deliver 0.55W to the 8 Omega load with a 3.3V supply voltage with 150-nm CMOS process. The power efficiency is over 90% and the output THD is smaller than 0.01% (80dB).
A Near-Optimum Dynamic Voltage Scaling (DVS) in 65-nm Energy-Efficient Power Management With Frequency-Based Control (FBC) for SoC System
(2012-11-01)
Lee, Yu-Huei
;
Chiu, Chao-Chang
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Peng, Shen-Yu
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Chen, Ke-Horng
;
Lin, Ying-Hsi
A 65-nm energy-efficient power management with frequency-based control (FBC) is proposed to achieve the near-optimum dynamic voltage scaling (DVS) in a system-on-chip system. Since DVS and dynamic frequency scaling (DFS) operations are demanded for system processor, control loop of the proposed single-inductor dual-output (SIDO) power module is merged with the frequency-controlled phase-locked loop (PLL) to constitute the operation of hybrid control loop. This means that both DVS and DFS operations can be guaranteed and are not affected by process, supply voltage, and temperature variations. The proposed power management can receive the demand of system processor by hybrid control loop and can help realize the supply voltage with different operation tasks for near-optimum DVS operation. The fabricated chip occupies a 1.12-mm(2) silicon area. Experimental results show that the SIDO power module achieves a peak efficiency of 90% and the highest power reduction of 33% with the proposed near-optimum DVS operation.
A Pseudo Fixed Switching Frequency 2kHz/A in Optimum On-Time Control Buck Converter with Predicting Correction Technique for EMI Solution
(2014-01-01)
Chen, Wei-Chung
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Lin, Kuei-Liang
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Chen, Ke-Horng
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Lin, Ying-Hsi
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Tsai, Tsung-Yen
This paper repots an optimum on-time (OOC) control with predicting correction technique (PCT) for ripple-based buck converter. The switching frequency (F-SW) variation is analyzed with completely considering the parasitic resistances of the components and devices. The proposed converter achieved nearly constant switching frequency over a wide load range without extra clock controlled circuits and current sensing circuits. The parameters of the parasitic resistances almost cause no influence and no restriction on F-SW performance. Actually, only the input voltage is necessary to predict the optimum on-time, and this work benefits the decease on total pin numbers. The simulation results demonstrate 0.375% Delta F-SW/F-SW and 2kHz/A Delta F-SW/Delta I-LOAD over 1.5A load current change. Consequently, pseudo constant F-SW with known noise spectrum strongly benefits the solution of electromagnetic interference (EMI) issue for system-on-chip (SoC).
A Single-Inductor Dual-Output Converter with Switchable Digital-or-Analog Low-Dropout Regulator for Ripple Suppression and High Efficiency Operation
(2012)
Lee, Yu-Huei
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Chen, Wei-Chung
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Chiu, Chao-Chang
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Peng, Shen-Yu
;
Chu, Kuan-Yu
a single-inductor dual-output (SIDO) converter with the switchable digital-or-analog (D/A) low-dropout (LDO) regulator achieves an analog dynamic voltage scaling (ADVS) function for ripple suppression and high efficiency in system-on-achip (SoC). The ADVS function helps dynamically adjust the dropout voltage of the switchable D/A LDO regulator with analog operation for ripple suppression according to the load current. On other hand, the switchable D/A LDO regulator activates the digital operation for high efficiency at light loads since the dropout voltage of the LDO regulator can be further reduced. Besides, the bidirectional asynchronous signal pipeline (BASP) can realize the 50nA quiescent current in digital LDO regulator. This chip was fabricated by the 40 nm CMOS process. Experimental results demonstrate the switchable LDO regulator operation with the peak efficiency of 92% and the 7 mV output voltage ripple at 200 mA load because of the ripple suppression. The efficiency can be kept higher than 83% even the load current is 1 mA.
An Embedded Dynamic Voltage Scaling (DVS) System Through 55 nm Single-Inductor Dual-Output (SIDO) Switching Converter for 12-Bit Video Digital-to-Analog Converter
(2012-07-01)
Chou, Wen-Shen
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Huang, Tzu-Chi
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Lee, Yu-Huei
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Yang, Yao-Yi
;
Su, Yi-Ping
"This paper proposes a 55 nm CMOS 12-bit current- steering video digital-to-analog converter (DAC) directly powered by the single-inductor dual-output (SIDO) switching converter to compose a dynamic voltage scaling (DVS) system and improve the power efficiency. Dual-DVS control in both digital and analog circuits can effectively reduce power consumption. With various supply voltages, the video DAC can meet several different specifications in the power optimized (PO) mode. Furthermore, for DAC, the proposed 3S method, including finger separating, splitting and shifting, achieves good differential nonlinearity (DNL) performance to 0.78/0.4 least significant bit (LSB) and integral nonlinearity (INL) 1.3/1.0 LSB (with/without SIDO converter) without additional calibration. It also suppresses the switching noise interference from the SIDO converter. Moreover, for SIDO converter, the cross-regulation performance is greatly improved in both transient and steady state to achieve lowest interference for the analog supply. The total power efficiency can be improved up to 11.5% and 28% in the DVS and the PO mode. The SIDO supplied DAC with the dual-DVS function achieves 69.88 dB spurious free dynamic range (SFDR) at the 1 V output swing and 1 MHz input. The proposed intrinsic 12-bit DAC and SIDO converter achieve high definition video DAC performance with the benefit of area and energy efficiency."
An Interleaving Energy-Conservation Mode (IECM) Control in Single-Inductor Dual-Output (SIDO) Step-Down Converters with 91% Peak Efficiency
(2010)
Lee, Yu-Huei
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Chen, Ke-Horng
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Lin, Ying-Hsi
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Yang, Yao-Yi
;
Wang, Shih-Jung
This interleaving energy-conservation mode control for single-inductor dual-output converter uses the superposition technique to yield the optimal average inductor current and 91% peak efficiency. Neither a freewheel stage nor a post-regulator is needed at nominal conditions. The output voltage ripple appears notably minimized over 50% by means of current interleaving at full load. The chip occupies 1.44 mm(2) in 65 nm CMOS and integrates with a 3D architecture for ultra-wide band system.
Dynamic Bootstrap Voltage Technique for High Efficiency Buck Converter in Universal Serial Bus Power Device Supplying System
(2013)
Chen, Wei-Chung
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Chen, Ke-Horng
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Wey, Chin-Long
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Lin, Ying-Hsi
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Tsai, Tsung-Yen
for high power universal serial bus (USB) devices, the dynamic bootstrap voltage (DBV) technique is proposed to keep high efficiency over a wide load range, including light and heavy loads. Besides, the silicon area of power management of the system-on-a-chip (Soc) can be effectively reduced to 50% of conventional design with P-type high-side power MOSFET. The test chip fabricated in 0.25 mu m CMOS process shows 92% peak efficiency from 1mA to 1A. The maximum driving current is higher than 3A with 88 % efficiency. Compared to that without the DBV technique, the efficiency is improved about 28%.
Instruction-Cycle-Based Dynamic Voltage Scaling Power Management for Low-Power Digital Signal Processor With 53% Power Savings
(2013-11-01)
Peng, Shen-Yu
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Huang, Tzu-Chi
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Lee, Yu-Huei
;
Chiu, Chao-Chang
;
Chen, Ke-Horng
This paper presents and analyzes a fully digital instruction-cycle-based dynamic voltage scaling (iDVS) power management strategy for low-power processor designs. The proposed iDVS technique is fully compatible with conventional DVS scheduler algorithms. An additional computer aided design-based design flow was embedded in a standard cell library to implement the iDVS-based processor in highly integrated system-on-a-chip applications. The lattice asynchronous self-timed control digital low-dropout regulator with swift response and low quiescent current was also utilized to improve iDVS voltage transition response. Results show that the iDVS-based processor with the proposed adaptive instruction cycle control scheme can efficiently perform millions of instructions per second during iDVS transition. The iDVS-based digital signal processor chip was implemented in a HH-NEC 0.18-mu m standard complementary metal-oxide semiconductor. Measurement results show that the voltage tracking speed with 11.6 V/mu s saved 53% power.
Interleaving Energy-Conservation Mode (IECM) Control in Single-Inductor Dual-Output (SIDO) Step-Down Converters With 91% Peak Efficiency
(2011-04-01)
Lee, Yu-Huei
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Yang, Yao-Yi
;
Wang, Shih-Jung
;
Chen, Ke-Horng
;
Lin, Ying-Hsi
The proposed single-inductor dual-output (SIDO) converter with interleaving energy-conservation mode (IECM) control is designed using 65 nm technology to power the ultra-wide band (UWB) system. The energy-conservation mode (ECM) control generates four different energy delivery paths for dual buck outputs with only one inductor. In addition, the superposition technique is used to achieve a minimized inductor current level. The average inductor current is equal to the summation of two output loads. Moreover, the IECM control activates the interleaving operation through the current interleaving mechanism to provide large driving capability as well as to reduce the output voltage ripple. As a result, 91% peak efficiency is derived and the output voltage ripple appears notably minimized by 50% using current interleaving at heavy load. The test chip occupies 1.44 mm(2) in 65 nm CMOS and integrates with a three-dimensional (3-D) architecture for inductor integration.
Minimized Transient and Steady-State Cross Regulation in 55-nm CMOS Single-Inductor Dual-Output (SIDO) Step-Down DC-DC Converter
(2011-11-01)
Lee, Yu-Huei
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Huang, Tzu-Chi
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Yang, Yao-Yi
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Chou, Wen-Shen
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Chen, Ke-Horng
A single-inductor dual-output (SIDO) step-down DC-DC converter with continuous conduction mode (CCM) operation is proposed to achieve an area-efficient power management module. The low-voltage energy distribution controller (LV-EDC) can simultaneously guarantee good voltage regulation and low output voltage ripple. With the proposed dual-mode energy delivery methodology, cross regulation in steady-state output voltage ripple, which is rarely discussed, and cross regulation in load transient response are both effectively reduced. In addition, the energy mode transition operation helps obtain the appropriate energy operation mode using the energy delivery paths for dual outputs. Moreover, within the allowable output voltage ripple, the automatic energy bypass (AEB) mechanism can reduce the number of energy delivery paths, thereby ensuring voltage regulation and further enhancing efficiency. The test chip, fabricated in 55-nm CMOS, occupies 1.44 mm(2) and achieves 91% peak efficiency, low output voltage ripple, and excellent load transient response for a high-efficiency system-on-a-chip (SoC) integration.
Real-Time Instruction-Cycle-Based Dynamic Voltage Scaling (iDVS) Power Management for Low-Power Digital Signal Processor (DSP) with 53% Energy Savings
(2012)
Peng, Shen-Yu
;
Lee, Yu-Huei
;
Wu, Chun-Hsien
;
Huang, Tzu-Chi
;
Chen, Ke-Horng
this paper presents an instruction-cycle-based dynamic voltage scaling (iDVS) power management strategy for a low-power processor design. The iDVS technique is fully compatible with conventional DVS scheduler algorithms. Furthermore, an additional iDVS design flow embedded in the standard cell lib flow is proposed to implement the iDVS-based DSP. In addition, the fast-response bidirectional asynchronous wave-pipeline (BAWP) digital low-dropout (LDO) regulator is also presented to improve the iDVS performance. The iDVS-based DSP chip implemented in an HH-NEC 0.18 mu m standard CMOS process demonstrates 53% energy savings over that without the iDVS technique.
Single Inductor Quad Output Switching Converter with Priority-Scheduled Program for Fast Transient and Unlimited-load Range in 40nm CMOS Technology
(2014-01-01)
Chen, Wei-Chung
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Huang, Tzu-Chi
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Tsai, Tsu-Wei
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Peng, Ruei-Hong
;
Lin, Kuei-Liang
System-on-a-chip (SoC) applications need multiple power supplies with low noise for analog circuits and high efficiency for digital circuits. Thus, this paper proposes the priority-scheduled program (PSP) for single inductor quad output (SIQO) switching converter to manage energy delivery for four outputs. Consequently, SIQO converter with PSP can provides fast transient response and reduce cross-regulation. Besides, the level bypass detector (LBD) provides unlimited load range between each output through the shared inductor. The PSP cooperates with the LDB to transfer energy to low priority outputs to avoid overshoot at high priority outputs. With the two low-dropout regulator (LDR) working as buffers at low priority outputs, voltage disturbance can be filtered out. The SIQO converter fabricated in 40nm CMOS technology satisfies power requirements in portable electronics with 0.2% low noise, 15 mu s fast transient response, and cross-regulation smaller than 30mV.