Browsing by Author "Huang, Chen-Wei"

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A novel nanostructured supramolecular hydrogel self-assembled from tetraphenylethylene-capped dipeptides
(2016)
Yeh, Mei-Yu
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Huang, Chen-Wei
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Chang, Jui-Wen
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Huang, Yu-Tang
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Lin, Jhong-Hua
Herein, we report a tetraphenylethylene-diglycine (TPE-GG) hydrogelator from a systematic study of TPE-capped dipeptides with various amphiphilic properties. From a chemical design, we found that the hydrogelation of TPE-GG molecules can be utilized to generate supramolecular nanostructures with a large TPE-based nanobelt width (similar to 300 nm) and lateral dimension ratio (>30 fold). In addition, TPE-GG has the lowest molecular weight and minimum number of atoms compared to any TPE-capped peptide hydrogelator reported to date. This minimal self-assembled hydrogelator can fundamentally achieve the gel features compared with other TPE-capped peptides. A combined experimental and computational study indicates the pi-pi interactions, electrostatic interactions and hydrogen-bonding interactions are the major driving forces behind the formation of self-assembled nanobelts. This study demonstrates the importance of structure-property relationships and provides new insights into the design of supramolecular nanomaterials.
An Efficient Thermal Estimation Scheme for Microprocessors
(2014-01-01)
Huang, Pei-Shu
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Chen, Quan-Chung
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Huang, Chen-Wei
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Tsao, Shiao-Li
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資訊工程學系
In recent years, thermal management, which improves the reliability, performance, power leakage, etc. of modern microprocessors, has been the subject of numerous computer architecture and system software studies. To determine the detailed thermal distribution of a microprocessor is among the critical tasks for thermal management. However, because thermal modeling tools require considerable computation time and memory to simulate fine-grain thermal information, they may be unsuitable for dynamic thermal management and hardware implementation. This study proposes a novel model based on reduced resistance-capacitance (RC) networks for efficiently calculating the temperature of a microprocessor. The proposed model is compared with two existing thermal simulation tools, namely, HotSpot [1] and Temptor [2]. The experiment studies show that the results generated using the proposed model differ from those of the existing tools by only 0.5 to 1.5%. However, the suggested model can increase computation speeds by 5 to 9 times and 98 to 161 times that of Temptor and HotSpot, respectively. For the memory usage, the proposed model consumes merely 0.45% of the space used by the existing tools.
High-Level Energy Consumption Model of Embedded Graphic Processors
(2015)
Huang, Chen-Wei
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Chung, Yu-An
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Huang, Pei-Shu
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Tsao, Shiao-Li
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資訊工程學系
Embedded graphic processing unit (GPU) is an indispensable component in enabling real-time rendering and graphic applications on mobile devices. However, embedded GPU consumes a considerable energy [1] which is critical for battery-operated devices. To understand the energy consumption of a graphic application, conventional approaches suggested the energy model based on hardware performance counters. However, those low-level energy models are mainly derived from GPUs of desktop computers, and they cannot be applied to embedded GPUs directly and the low-level models are less intuitive from a programmer\'s point of view. In this study, we consider a high-level energy consumption model for embedded graphic processors, and then we can estimate energy consumption of a graphic application based on graphic attributes of a scene. We conduct a number of experiments on real platforms to validate the proposed model. Our experimental results demonstrate that an average energy estimation error rate of 7.30% can be achieved.
Minimizing Energy Consumption of Embedded Systems via Optimal Code Layout
(2012-08-01)
Huang, Chen-Wei
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Tsao, Shiao-Li
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資訊工程學系
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Department of Computer Science
Code repositioning is a well-known method of reducing inefficient off-chip memory accesses by streamlining cache behavior. Embedded systems with predetermined applications can achieve further improvement with the addition of fast and energy efficient scratchpad memory (SPM) on chip and moving frequent accesses code and/or data from main memory to SPM. While many researchers have attempted to either streamline cache accesses or improve the effectiveness of SPM, few studies focus on exploring their joint synergy. This study proposes integer linear programming (ILP) models that include both code repositioning and SPM code selection to identify the optimal code layout and reduce energy consumption in embedded systems with a cache and SPM. This study also proposes a two-stage metaheuristic algorithm. Experimental results reveal that 1) allocating a dedicated portion of the on-chip SRAM to the SPM is not always better than using a cache-only configuration and 2) it is not trivial to select code objects for the SPM. As much as 55 percent additional energy can be saved by applying both code repositioning and SPM code selection techniques.
Static WCET Analysis of the H.264/AVC Decoder Exploiting Coding Information
(2014-01-01)
Huang, Chen-Wei
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Kelter, Timon
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Boenninghoff, Bjoern
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Kleinsorge, Jan
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Engel, Michael
Multimedia playback programs must satisfy certain hard real-time constraints to give their user a pleasant viewing experience. Having a tight estimation on the worst case execution time (WCET) is essential for the resource scheduler to ensure all the tasks in the system can satisfy their timing requirements while maintaining good system resource utilization. In this paper we present a detailed hybrid WCET analysis of the H.264/AVC reference decoder and demonstrate that the coding information can be used to tighten the pure static WCET estimation up to 70%.
The Critical Grid Size and Transmission Radius for Local-Minimum-Free Grid Routing in Wireless Ad Hoc and Sensor Networks
(2010-12-01)
Yi, Chih-Wei
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Wan, Peng-Jun
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Su, Chao-Min
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Huang, Chen-Wei
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資訊工程學系
In grid routing, the plane is tessellated into equal-sized square cells. Two cells are called neighbor cells if they share a common edge, and two nodes are called routing neighbors if they are in neighbor cells and within each other's transmission range. If communication parties are in the same cell, packets can be transmitted directly; otherwise, packets are forwarded to routing neighbors that are in cells closer to destination cells. As a greedy strategy, grid routing suffers the existence of local minima at which no neighbor nodes exist for relaying packets. To guarantee deliverability, in this paper, we investigate two vital parameters of grid routing, called the grid size and the transmission radius. Assume that nodes are represented by a Poisson point process with rate n over a unit-area square, and let l denote the grid size and r the transmission radius. First, we show that if l = root beta ln n/n for some constant beta and r = root 5l, then beta = 1 is the threshold for deliverability. In other words, there almost surely do not exist local minima if beta > 1 and there almost surely exist local minima if beta < 1. Next, for any given beta > 1, we give sufficient and necessary conditions to determine the critical transmission radius (CTR) for deliverability. Then, we show that as beta congruent to 1.092, the CTR r congruent to 2.09 root ln n/nis the minimum over all beta > 1. Simulation results are given to validate this theoretical work.