Browsing by Author "Huang, Chi-Wei"

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A 2.36 mu W/Ch CMOS 8-Channel EEG Acquisition Unit with Input Protection Circuits for Applications Under Transcranial Direct Current Stimulation
(2019-01-01)
Wu, Chung-Yu
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Huang, Chi-Wei
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Tsai, Tzung-Lin
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A 0.18um-CMOS 8-channel EEG acquisition unit with input protection circuits is designed and fabricated for EEG monitoring under the transcranial direct current stimulation (tDCS). The capacitively-coupled chopper instrumentation amplifier (CCCIA) with chopper modulation is used to suppress flicker noise and amplify input EEG signals. To filter out high frequency noise with high linearity, the switched-capacitor low-pass filter (SC-LPF) is proposed. The switchedcapacitor amplifier (SC-Amp) is also proposed to drive ADC capacitor array. The input protection circuit (IPC) is implemented by I/O device to keep internal circuits from overstress and artifacts from the tDCS. A 10-bit SAR ADC with offset-calibration comparator is integrated for accurate ADC conversion. The fabricated EEG acquisition unit has programmable gain 57.5/67.6/78.5dB. The measured power dissipation of a single CCCIA circuit is 2.36 mu W per channel. The measured recovery time is 7.5ms after the tDCS stimulation. It has been verified that the designed chip can record real EEG signals.
An 1.97 mu W/Ch 65nm-CMOS 8-Channel Analog Front-End Acquisition Circuit with Fast-Settling Hybrid DC Servo Loop for EEG Monitoring
(2018-01-01)
Chen, Pin-Wen
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Huang, Chi-Wei
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Wu, Chung-Yu
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, a 65nm-CMOS 8-channel Analog Front-End (AFE) acquisition circuit is designed and fabricated for long term EEG monitoring. The Capacitively-Coupled Chopper Instrumentation Amplifier (CCCIA) with chopper modulation is used to amplify input EEG signals and suppress flicker noise. To realize low high-pass corner and large Electrode DC Offset (EDO) rejection ability, a fast-settling Hybrid DC Servo Loop (HDSL) is proposed here. It contains Digital DSL (DDSL) and Analog DSL (ADSL) to achieve better trade-off among power consumption, area, and hardware complexity. An energy-efficient 10-bit SAR ADC with offset-calibration comparator is integrated for accurate A/D conversion. The chip is fabricated in 65nm CMOS technology. The measured overall power dissipation of the acquisition circuit is 1.97 mu W per channel. The input-referred noise of AFE Amplifier (AFEA) is 0.7 mu V in pass band, and the Noise Efficient Factor (NEF) of the CCCIA is 1.99. The measured HDSL calibration time is 125ms. The fabricated SAR ADC has the power consumption of 0.85 mu W under 1V supply and the SNDR of 59.8dB at 100kS/s with the Nyquist input frequency. This chip can record EEG signals successfully and the recorded signal has been verified by NeruScan SynAmps RT 64-channel amplifiers.
Anterior bone loss after cervical Bryan disc arthroplasty: insight into the biomechanics following total disc replacement
(2020-08-01)
Chen, Tse-Yu
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Chen, Wen-Hsien
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Tzeng, Chung-Yuh
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Huang, Chi-Wei
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Yang, Chih-Chang
BACKGROUND CONTEXT: Cervical disc arthroplasty (CDA) is an innovative procedure launched in the early 2000s. Compared with anterior cervical discectomy and fusion, many studies show that CDA offers equivalent clinical outcomes while reducing secondary procedures and total cost. PURPOSE: We sought to determine the incidence of anterior bone loss after CDA and the related biomechanical effects. STUDY DESIGN/SETTING: Retrospective chart review. PATIENT SAMPLE: Patients who underwent CDA with one level Bryan Disc (Medtronic SofamorDanek, Memphis, TN, USA) at one institution. OUTCOME MEASURES: Radiological measurements, including the extent of anterior bone loss, global alignment angle, shell angle, lordotic angle, mean degree of angle of the endplate with the horizontal line, global range of motion (ROM) and ROM of the index level were recorded. The grading of anterior bone loss of the index level was defined as Grade 0, no remodeling; Grade 1, spur disappearance or mild change in body contour; Grade 2, obvious bone regression with Bryan Disc exposure. METHODS: Anatomical measures and ROM were compared by grade of bone loss. RESULTS: Of the 121 patients included in the study, anterior bone loss was found in 53 (43.8%) on the upper adjacent level and 54 (44.6%) on the lower adjacent level. Twenty-nine patients (23.9%) had anterior bone loss in both levels. The majority of cases had Grade 1 anterior bone loss. Grade 2 bone loss was noted in the upper adjacent vertebra in only 5 patients and in 4 patients in the lower adjacent vertebra. Age, sex, operative level, and hybrid surgery had no effect on anterior bone loss. Most radiological assessments, including global alignment angle, lordotic angle, mean degree of angle of the endplate with the horizontal line, global ROM, and ROM of the index level, showed no correlation to anterior bone loss. Shell angle was found to be different in groups with or without remodeling in the upper adjacent level: 5.0 degreesin the Grade 0 group and 7.0 degrees in the Grade 1-2 group, p<. 05. CONCLUSIONS: Many more patients than predicted had anterior bone loss. Increasing the shell angle of the artificial disc may increase the incidence of anterior bone loss after CDA. Further study of the biomechanics following CDA should help clarify the mechanisms at work. (c) 2020 The Authors. Published by Elsevier Inc. This is an open access article under the CC BY-NC-ND license. (http://creativecommons.org/licenses/by-nc-nd/4.0/)
The Design of CMOS Electrode-Tissue Impedance Measurement Circuit Using Differential Current Switch with CMFB Bias for Implantable Neuro-Modulation SoCs
(2019-01-01)
Huang, Chi-Wei
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Chung, Chi-Heng
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Syu, Ruei-Syuan
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Wu, Chung-Yu
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交大名義發表
A new electrode-tissue impedance measurement circuit integrated with a System-on-Chip (SoC) is proposed and designed for implantable medical devices to monitor the electrode-tissue contact status. In the proposed circuit, a differential step current is injected into the electrode-tissue structure to generate a voltage. A differential current switch with a common-mode feedback (CMFB) bias circuit and shaped control signals are designed to generate accurate step currents and stable common-mode bias voltage. Moreover, the measurement circuit shares part of the bio-signal acquisition circuit in the SoC. Thus only an extra power dissipation of 4.3 mu W is needed at the operating frequency of 15.625Hz. The proposed circuit is fabricated by 0.18 um CMOS technology. The measurement results have shown that the resolution is 17 Omega(pp) and the maximum error is 3.4% for an impedance of 46k Omega. The proposed circuit is also verified in an in-vitro test by measuring the electrode-tissue impedance of a subdural grid electrode sunk in the phosphate buffered saline (PBS) buffer.