Browsing by Author "Huang, Chien-Chia"

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A Learning-Based Methodology for Routability Prediction in Placement
(2018-01-01)
Chen, Li-Chin
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Huang, Chien-Chia
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Chang, Yao-Lin
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Chen, Hung-Ming
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電子工程學系及電子研究所
The mutability of a circuit is a critical challenge due to the complexity of design rules. Global routing produces a congestion map on a coarse grid and feeds the results to the placer to optimize the design for reducing detailed-route DRC violations. However, there is a growing gap between global routing and the actual violations in detailed routing. This miscorrelation may end up unroutable for back-end detailed routing. In this work, a methodology as well as the framework How based on machine learning technique is proposed to effectively predict detailed routing violations. After extracting appropriate features from placement, fast global routing and detailed routing violations, we use support vector machine techniques to train the prediction model, different from regression framework. We then also develop a prediction model for DRC violation density which can be integrated into placers. Experimental results show that the proposed approach can effectively forecast routability during placement stage.
Functional Canonical Analysis Between Functional and Interval Data
(2009)
Jou, Yow-Jen
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Huang, Chien-Chia
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Wu, Jennifer Yuh-Jen
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資訊管理與財務金融系註：原資管所+財金所
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Department of Information Management and Finance
In this study we discuss the functional canonical correlation analysis between the functional data and the interval data. To address the interval data, a representative is of necessity. Based on the work by Chavent et al. (2002), the representative can be derived by using the Hausdorff distance between intervals. The canonical analysis can be either the mixed functional-multivariate canonical correlation analysis or a pure functional one. This approach is then applied to the roadside vehicle detection by using Radar devices. It can be observed that the weight functions implicitly contain the information about the distances between the specific lane and the detector.
Heterogeneous Chip Power Delivery Modeling and Co-Synthesis for Practical 3DIC Realization
(2017-01-01)
Liao, Wei-Hsun
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Lin, Chang-Tzu
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Fang, Sheng-Hsin
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Huang, Chien-Chia
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Chen, Hung-Ming
Three dimensional IC (3DIC) is becoming practical in today's consumer electronics designs. However, one major problem remains in design synthesis and flow: how to model heterogeneous die(s) with major logic die for power synthesis and signoff. This work provides a realistic model and principle for heterogeneous dies power network for 3DICs. It is based on given abstract or early stage information like bump location and power consumption from the provider. Our work also uses this model to synthesize power network with bottom logic die in the design flow. The result is DRC clean power network without IR and EM violation for all power domains. First, we analyze the location and power consumption of power bump for heterogeneous die(s). Second, according to previous analysis, we decide the stripe location and power sink location of heterogeneous dies model by a clustering method. After the initial model is synthesized, we convert it to a node graph with corresponding resistance of via and metal layer, also nodal voltages. Third, the model is optimized by using Sequential Linear Programming (SLP) to adjust stripe width. It will improve the model iteratively until the target IR-Drop is met. Furthermore, our work will create a pseudo DEF of the proposed model to be incorporated with the commercial tool for verification. We experiment on a real case from design house containing a 3D DRAM stack to demonstrate the effectiveness of this cross-layer realization. Results show that we can save 34% metal layer usage in one of the power domains in our case by using proposed methodology.
Late Breaking Results: An Efficient Learning-based Approach for Performance Exploration on Analog and RF Circuit Synthesis
(2019-01-01)
Pan, Po-Cheng
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Huang, Chien-Chia
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Chen, Hung-Ming
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
An efficient synthesis technique for modern analog circuits is important yet challenging due to the repeatedly re-synthesis process. To precisely explore the analog circuit performance limitation on the required technology is time-consuming. This work presents a learning-based framework for searching the limitation of analog circuits. With hierarchical architecture, the dimension of solution space can be reduced. Bayesian linear regression and support vector machine model are selected to speed up the algorithm and better performance quality can be retrieved. Experimental results show that our approach on two analog circuits can achieve up to 9x runtime speed-up without surrendering performance qualities.
On Closing the Gap Between Pre-simulation and Post-simulation Results in Nanometer Analog Layouts
(2018-01-01)
Pan, Po-Cheng
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Huang, Hung-Wen
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Huang, Chien-Chia
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Patyal, Abhishek
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Chen, Hung-Ming
In order to generate analog layout in advanced technology, it still remains lots of challenges due to the imprecise estimation of critical performance parameters. We propose an upgraded decision making framework, PEDefer, to decompose existing layout into decisive components for performance estimation. In this work, the objective is to synthesize layout solutions based on the performance estimation of user-defined constraints and existing templates. The constraints of the circuit are priorly tackled in the partition and layout enumeration stage. In addition, we attempt to have partial layout pieces as exchangeable blocks to perform pseudo-post-simulation, thus to put simulation factors in the evaluation during layout enumeration strategy. The experiments show that this flow guarantees valid analog layout results whose performances are closer to netlist-level simulation than manual designed or migrated layouts with minimal overhead.
Semi-parametric linear mixed effects model for vehicles identification
(2007)
Jou, Yow-Jen
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Yang, Chai-Tzu
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Huang, Chien-Chia
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Wu, Jennifer Yuh-Jen
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資訊管理與財務金融系註：原資管所+財金所
In order to make the detecting of the lanes and the types of the vehicles traveling on various roadways affordable, radio-frequency (RF) system-on-chip is designed and will be mounted on the roadside to collect vehicle information. We use the Fast Fourier Transform (FFT) to transform the signal of the reflecting wave radar into the numerical data, and utilize it by the statistical approach to discriminate the size of cars and the lanes. In order to classify the types of the vehicles, two models are proposed to model the data. One is multivariate analysis of variance model to account for the main effect and the interaction effect between type and lane, the other is the semi-parametric linear mixed effect model to emphasize the functional characteristic of the data. Both models work well when the number of groups is small but deteriorate when the number of groups increases.