Browsing by Author "Huang, Chien-Chih"

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Effect of novel atmospheric-pressure jet pretreatment on the drying kinetics and quality of white grapes
(2019-08-30)
Huang, Chien-Chih
;
Wu, James Swi-Bea
;
Wu, Jong-Shinn
;
Ting, Yuwen
;
機械工程學系
BACKGROUND Raisin is a popular snack and a common constituent of many foods owing to its good flavor and nutritional value. Conventional drying of grapes can be a slow and energy-consuming process as their waxy surface hinders efficient moisture migration. A drying pretreatment that disrupts the waxy cuticle is usually applied to increase the drying rate. RESULTS The application of an atmospheric-pressure air plasma jet to the grape surface could effectively enhance the drying kinetics and decrease the drying time by more than 20%. Through etching of the waxy cuticle, the air plasma jet optimally improves the quality of the final product. Although the surface hydrophilicity was increased by 40%, the physical appearance, color, and texture of plasma-treated raisins were similar to the product from untreated control and chemical-treated groups. A more than twofold increase in the total phenolic content and antioxidant capacity was observed when compared to other experimental groups. CONCLUSIONS The results indicate that atmospheric plasma could be a better option than using chemicals to pretreat grapes before drying since it leaves no toxic residue, while successfully preserving the product quality. This work shows the great potential for the application of atmospheric air plasma in the drying of food materials. (c) 2019 Society of Chemical Industry
Nonlinear Dynamics of Semiconductor Lasers Under Repetitive Optical Pulse Injection
(2009-05-01)
Lin, Fan-Yi
;
Tu, Shiou-Yuan
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Huang, Chien-Chih
;
Chang, Shu-Min
;
應用數學系
In this paper, nonlinear dynamics of semiconductor lasers under repetitive optical pulse injection are studied numerically. Different dynamical states, including pulsation and oscillation states, are found by varying the intensity and the repetition rate of the injection pulses. The laser is found to enter the chaotic pulsation (CP) states and chaotic oscillation (CO) states through individual period-doubling routes. Mapping and corresponding Lyapunov exponents of these dynamical states are plotted and examined in the parameter space. Moreover, the bandwidths of the chaos states found are investigated, where the bandwidths of the CP states observed at the strong injection regime are two to four times broader than the bandwidths of the CO states found at the weak injection regime. In this paper, frequency-locked states with different winding numbers, the ratio of the oscillation frequency, and the repetition frequency of the injection pulses are also studied. Both the cases for repetition frequency above and below the relaxation oscillation frequency are examined. The winding numbers of the frequency-locked states reveal a Devil's staircase structure, where a Farey tree showing the relations between the neighboring states is constructed.
Optimal Common-Centroid-Based Unit Capacitor Placements for Yield Enhancement of Switched-Capacitor Circuits
(2013-12-01)
Huang, Chien-Chih
;
Wey, Chin-Long
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Chen, Jwu-E
;
Luo, Pei-Wen
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電機工程學系
Yield is defined as the probability that the circuit under consideration meets with the design specification within the tolerance. Placement with higher correlation coefficients has fewer mismatches and lower variation of capacitor ratio, thus achieving higher yield performance. This study presents a new optimization criterion that quickly determines if the placement is optimal. The optimization criterion leads to the development of the concepts of C-entries and partitioned subarrays which can significantly reduce the searching space for finding the optimal/near-optimal placements on a sufficiently large array size.
PACES: A Partition-Centering-Based Symmetry Placement for Binary-Weighted Unit Capacitor Arrays
(2017-01)
Huang, Chien-Chih
;
Chen, Jwu-E
;
Wey, Chin-Long
;
電機工程學系
;
Department of Electrical and Computer Engineering
Capacitor matching influences linearity performance, which is a critical measure of analog-to-digital converters (ADCs). Various placement techniques have been proposed to eliminate both systematic and random mismatches of capacitor pairs. However, a placement technique that eliminates capacitor mismatches may not result in good linearity performance for successive-approximation-register ADCs because their linearity performance is related to the accuracy of their binary-weighted continued ratio. This paper addresses the critical problem of placement estimation based on ratio mismatch M, overall correlation coefficient L, and performance metrics. A low M and a high L value do not imply higher linearity performance. Therefore, we propose a partition-centering-based symmetry placement algorithm for the layout considering parasitic capacitance matching. The experimental results show that the proposed placement approach can achieve higher linearity performance and a shorter placement generation time compared with the conventional approach.
Performance-Driven Unit-Capacitor Placement of Successive-Approximation-Register ADCs
(2015-11)
Huang, Chien-Chih
;
Wey, Chin-Long
;
Chen, Jwu-E
;
Luo, Pei-Wen
;
電子工程學系及電子研究所
The performance of many switched-capacitor analog integrated circuits, such as analog-to-digital converters (ADCs) and sample and hold circuits, is directly related to their accurate capacitance ratios. In general, capacitor mismatch can result from two sources of errors: random mismatch and systematic mismatch. Paralleling unit capacitance (UC) with a common-centroid structure can alleviate the random mismatch errors. The complexity of generating an optimal solution to the UC placement problem is extremely high, let alone if both placement and routing problems are to be optimized simultaneously. This article evaluates the performance of the UC placement generated in an existing work and proposes an alternative UC placement to achieve optimal ratiomismatch M and better linearity performance of SAR ADC design. Results show that the proposed UC placement achieves a ratio mismatch of M = 0.695, the effective number of bits ENOB = 8.314 bits, and the integral nonlinearity INL = 0.816 LSB (least significant bits) for a 9-bit SAR ADC design.