Browsing by Author "Huang, Chin-Yuan"

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Detecting Stability Faults in Sub-threshold SRAMs
(2011)
Lin, Chen-Wei
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Yang, Hao-Yu
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Huang, Chin-Yuan
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Chen, Hung-Hsin
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Chao, Mango C. -T.
Detecting stability faults has been a crucial task and a hot research topic for the testing of conventional super-threshold 6T SRAM in the past. When lowering the supply voltage of SRAM to the subthreshold region, the impact of stability faults may significantly change, and hence the test methods developed in the past for detecting stability faults may no longer be effective. In this paper, we first categorize the subthreshold-SRAM designs into different types according to their bit-cell structures. Based on each type, we then analyze the difference of its stability faults compared to the conventional super-threshold 6T SRAM, and discuss how the stability-fault test methods should be modified accordingly. A series of experiments are conducted to validate the effectiveness of each stability-fault test method for different types of subthreshold-SRAM designs.
Fault Models and Test Methods for Subthreshold SRAMs
(2013-03-01)
Lin, Chen-Wei
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Chen, Hung-Hsin
;
Yang, Hao-Yu
;
Huang, Chin-Yuan
;
Chao, Mango C. -T.
Due to the increasing demand of an extra-low-power system, a great amount of research effort has been spent in the past to develop an effective and economic subthreshold SRAM design. However, the test methods regarding those newly developed subthreshold SRAM designs have not yet been fully discussed. In this paper, we first categorize the subthreshold SRAM designs into three types, study the faulty behavior of open defects and address decoders faults on each type of designs, and then identify the faults which may not be covered by a traditional SRAM test method. We will also discuss the impact of open defects and threshold-voltage mismatch on sense amplifiers under subthreshold operations. A discussion about the temperature at test is also provided.
Testing of a Low-V-MIN Data-Aware Dynamic-Supply 8T SRAM
(2013)
Lin, Chen-Wei
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Huang, Chin-Yuan
;
Chao, Mango C. -T.
;
電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Due to the demand of lower power, a lot of research effort has been devoted into developing new SRAM cell designs that can operate with low supply voltage. The new SRAM cell designs have their own cell structures and design techniques, which may result in different faulty behaviors than the conventional 6T SRAM. Accordingly, specialized test methods are usually required for the uncovered faults of traditional tests. In this paper, we focus on testing open defects in a new low-V-MIN data-aware dynamic-supply 8T SRAM design. The new SRAM utilizes a data-aware dynamic-supply circuitry cooperating with two write-word-lines to assist the write and an independent read path to enhance the read-SNM. Based on the specific cell structure, we propose a novel test method for the open defects. The test method creates an in-cell self-attacking environment and can detect all the defects undetected by traditional tests in both the SRAM cell and the data-aware dynamic-supply circuitry. Also, the method requires much less test time when being compared to the traditional floating bit-line attacking method.