Browsing by Author "Huang, Chung-Kai"

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Effective Passivation With High-Density Positive Fixed Charges for GaN MIS-HEMTs
(2017-05-01)
Liu, Shih-Chien
;
Huang, Chung-Kai
;
Chang, Chia-Hua
;
Lin, Yueh-Chin
;
Chen, Bo-Yuan
An effective passivation with high-density positive fixed charges was demonstrated on GaN MIS-HEMTs. The positive fixed charges at the interface between passivation and AlGaN surface can reduce the surface potential and expand the quantum well under Fermi level. Besides, to satisfy charge balance, the net charge density at the AlGaN surface must equal to the 2DEG carrier density. Thus, the positive fixed charges passivation can increase the 2DEG carrier density and improve the switching performance of GaN MIS-HEMTs. In this paper, we demonstrated a high-density positive fixed charges (similar to 2.71 x 10(13) e/cm(-2)) passivation using SiON for GaN MIS-HEMTs. The device with SiON passivation exhibits significant improvements in I-V characteristics and dynamic R-ON compared to the conventional SiN passivated device.
Effective surface treatment for GaN metal-insulator-semiconductor high-electron-mobility transistors using HF plus N-2 plasma prior to SiN passivation
(2016-01-01)
Liu, Shih-Chien
;
Trinh, Hai-Dang
;
Dai, Gu-Ming
;
Huang, Chung-Kai
;
Dee, Chang-Fu
An effective surface cleaning technique is demonstrated for the GaN metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) passivation process. In this study, dilute HF solution and in situ N-2 plasma treatments were adopted to remove the native oxide and recover the nitrogen-vacancy defects at the GaN surface before device passivation. To investigate the correlation between the properties of the SiN/GaN interface and the device performance, the GaN MIS-HEMTs were characterized using current-voltage (I-V) measurement, capacitance-voltage (C-V) measurement, and X-ray photoelectron spectroscopy (XPS) analysis. With the application of this surface treatment technique, the device exhibits improved I-V characteristics with low leakage current, low dynamic ON-resistance, and good C-V response with a steep slope. Overall, the results reveal that the oxide-related bonds and nitrogen-vacancy defects at the SiN/GaN interface are the root cause of the GaN MIS-HEMTs performance degradation. (C) 2016 The Japan Society of Applied Physics
Effective surface treatment for GaN metal-insulator-semiconductor high-electron-mobility transistors using HF plus N-2 plasma prior to SiN passivation
(2016-01)
Liu, Shih-Chien
;
Trinh, Hai-Dang
;
Dai, Gu-Ming
;
Huang, Chung-Kai
;
Dee, Chang-Fu
An effective surface cleaning technique is demonstrated for the GaN metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) passivation process. In this study, dilute HF solution and in situ N-2 plasma treatments were adopted to remove the native oxide and recover the nitrogen-vacancy defects at the GaN surface before device passivation. To investigate the correlation between the properties of the SiN/GaN interface and the device performance, the GaN MIS-HEMTs were characterized using current-voltage (I-V) measurement, capacitance-voltage (C-V) measurement, and X-ray photoelectron spectroscopy (XPS) analysis. With the application of this surface treatment technique, the device exhibits improved I-V characteristics with low leakage current, low dynamic ON-resistance, and good C-V response with a steep slope. Overall, the results reveal that the oxide-related bonds and nitrogen-vacancy defects at the SiN/GaN interface are the root cause of the GaN MIS-HEMTs performance degradation. (C) 2016 The Japan Society of Applied Physics
Halbleitervorrichtung und Verfahren zur Herstellung derselben
(2018-06-21)
CHANG EDWARD YI
;
LIU SHIH-CHIEN
;
HUANG CHUNG-KAI
;
WU CHIA-HSUN
;
HAN PING-CHENG
A semiconductor device includes a substrate, a channel layer, a barrier layer, a recess, a charge trapping layer, a ferroelectric material layer, a gate, a source and a drain. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The barrier layer has a recess, and a portion of the barrier layer under the recess has a thickness. The source and the drain are disposed on the barrier layer. The charge trapping layer covers the bottom of the recess. The ferroelectric material is disposed on the charge trapping layer. The gate is disposed on the ferroelectric material.