Browsing by Author "Huang, G. -W."

Now showing 1 - 9 of 9

2.4/5.7-GHz Dual-Band Dual-Conversion Low-IF Downconverter Using 0.35 mu m SiGe HBT Technology
(2010)
Syu, J. -S.
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Meng, C. C.
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Yu, S. -W.
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Huang, G. -W.
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電機工程學系
A 2.4/5.7-GHz dual-band dual-conversion low-IF downconverter is demonstrated using 0.35 mu m SiGe heterojunction bipolar transistor (HBT) technology. The first image signal is shifted away from the IF band by a complex Weaver architecture while the second image signal is eliminated by a complex Hartley architecture. The downconverter achieves a 45/44-dB image-rejection ratio of the first image (IRR1) and a 50/48-dB image-rejection ratio of the second image (IRR2) for 2.4/5.7-GHz modes, respectively, when IF frequency ranges from 20 to 40 MHz.
5 GHz quadrature voltage-controlled oscillator using trifilar transformers
(2008-04-24)
Syu, J. -S.
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Meng, C.
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Tsung, K. -C.
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Huang, G. -W.
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電信工程研究所
A 0.18 mm CMOS 5 GHz quadrature voltage-controlled oscillator (QVCO) is demonstrated by using trifilar transformer coupling. The trifilar transformers composed of one primary coil and two secondary coils are used to separate the gate and drain bias for output voltage swing optimisation and also replace a conventional transistor-coupling method for quadrature output generation simultaneously. As a result, the trifilar-coupling QVCO achieves 180.1 dBc/Hz figure of merit (FOM) at the supply voltage of 1.2 V. The on-chip passive single sideband upconversion mixer is also demonstrated to fairly measure the quadrature accuracy of the QVCO. Thus, a 33.7 dB sideband rejection ratio is achieved.
A Comprehensive Study of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Layer Effects on Negative Capacitance FETs for Sub-5 nm Node
(2018-01-01)
Tang, Y. -T
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Su, C. -J.
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Wang, Y. -S.
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Kao, K. -H.
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Wu, T. -L.
The impact of a realistic representation of gate-oxide granularity on negative-capacitance (NC) FETs at sub-5nm node is studied by a newly developed thermodynamic energy model based on the first principle calculation (FPC). For the first time, the calculation fully couples the Landau-Khalatnikov (L-K) equation with grain-size effect equation in NC-FETs. It explains the experimental results in phase transition and reveals excellent immunity against depolarization in ferroelectric (FE) layer owing to dopant concentration and stress in thin films. A sub-5nm node (L-G=10nm) NC-FET with thin FE layer (T-FE similar to 2nm) is integrated to achieve low subthreshold slope (SS) of 52mV/dec via a 1.9GPa-tensor stressed interfacial layer (IL) and 12% Zr-doped HfO2.
A Unique Approach to Generate Self-Aligned T-Gate Transistors in Counter-Doped Poly-Si With High Etching Selectivity and Isotropy
(2020-03-01)
Huang, Y. -A.
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Liang, C. -Y.
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Peng, K. -P.
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Chen, K. -M.
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Huang, G. -W.
A unique approach for fabricating poly-Si thin-film transistors (TFTs) with self-aligned T-shaped gate (T-gate) structure is reported. A counter-doped poly-Si process comprises an in-situ doped n(+) poly-Si deposition followed by a subsequentshallow implantation of BF2+. Both high etching isotropy in n(+) poly-Si and high etching selectivity between n(+) poly-Si and B-doped poly-Si in a Cl-2-based plasma process are the key enablers for the fabrication of our T-gate structures. Thanks to good control in the shape and deformation of our T-gate structure, sidewall air-gap spacers in combination with self-aligned Ni silicided gate and source/drain were established. High-performance sub-micron poly-Si TFTs are evidenced by superior transfer characteristics measured on TFTs with effective gate length of 0.15 mu m . The unique T-gate structure provides an effective way for possible production of poly-Si radio-frequency TFTs viable for emerging new applications.
First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications
(2019-01-01)
Chang, S. -W.
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Sung, P. -J.
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Chu, T-Y.
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Lu, D. D.
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Wang, C. -J.
For the first time, CMOS inverters and 6T-SRAM cells based on vertically stacked gate-all-around complementary FETs (CFETs) are experimentally demonstrated. Manufacturing difficulties of vertically stacked source and drain electrodes of the CFETs have been overcome by using junctionless transistors, thereby reducing the number of lithographic steps required. Furthermore, with post metallization treatments, both the voltage transfer characteristics (VTCs) of CMOS inverters and butterfly curves of SRAM show significant improvements due to the symmetry of nMOS and pMOS threshold voltages. Simulation shows that 3-dimensional CFET inverters have lower input parasitic capacitance than standard 2-dimensional CMOS, leading to reduced gate delay and lower power consumption.
Gain enhancement techniques for CMOS LNA and mixer
(2006-10-01)
Su, J. -Y.
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Meng, C. C.
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Li, Y. -H.
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Tseng, S. -C.
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Huang, G. -W.
Two major techniques for gain improvement of the CMOS low noise amplifier (LNA) and mixer are presented. First, the inductive interstage matching is applied to design a cascode amplifier for increasing the power transfer between the common source (CS) and common gate (CG) stages. Second, a super source follower (SSF) is utilized in a P-type micromixer for increasing the conversion gain of the mixer. A series of investigations are performed for demonstrating the feasibilities of the proposed techniques. The LNA and mixer designs based on the proposed techniques are realized using 0.35 im IP4M CMOS technology. Then their measured results are compared with those of a preliminary design, which fully integrates a conventional cascode amplifier and a P-type micromixer. The gain of the LNA is increased 2.1 dB and the noise figure is maintained at the same value of the preliminary design. On the other hand, the conversion gain of the super source follower (SSF) of the micromixer output is improved about 9.5 dB. Such improvements reveal great potential of the proposed design techniques on the gain enhancement for the LNA and mixer. Then, the measured results of the preliminary design show the return-loss of 25 dB, the isolation of better than 30 dB, and the conversion gain of 4.8 dB in the 2.4 GHz ISM hand. (C) 2006 Wiley Periodicals, Inc.
Ge Nanowire FETs with HfZrOx Ferroelectric Gate Stack Exhibiting SS of Sub-60 mV/dec and Biasing Effects on Ferroelectric Reliability
(2017-01-01)
Su, C. -J.
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Hong, T. -C.
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Tsou, Y. -C.
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Hou, F. -J.
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Sung, P. -J.
Ge nanowire (NW) FETs exhibiting subthreshold swing (SS) of 54 mV/dec at room temperature are demonstrated with ferroelectric HfZrOx (FE-HZO) gate stack for the first time. I-ON/I-OFF ratios higher than 10(7) and 10(6) for p- and n-NWFETs, respectively, have been achieved by adopting the gate-all-around (GAA) configuration. Electrical biasing effects on the HZO ferroelectric reliability have been systematically investigated in this work. It is found that the polarization behavior will degrade with electrical stress time and can be recovered. The Ge HZO FinFET CMOS inverter shows experimentally voltage gain of 24.8 V/V.
High Performance Complementary Ge Peaking FinFETs by Room Temperature Neutral Beam Oxidation for Sub-7 nm Technology Node Applications
(2016-01-01)
Lee, Y. -J.
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Hong, T. -C.
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Hsueh, F. -K.
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Sung, P. J.
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Chen, C. -Y.
Ge peaking n- and p-FinFETs have been demonstrated by adopting neutral beam etching (NBE) and anisotropic neutral beam oxidation (NBO) processes. The irradiation-free NB processes not only suppress surface roughness but also guarantee low defect generation on the etched Ge surface. The fabricated Ge peaking FinFETs possess several unique features: (1) A peaking fin configuration with a 6-nm top-gate formed by an anisotropic NBO process at room temperature. (2) Nearly defect-free three dimensional channel surfaces by NB processes. (3) ION and Gm improvement by NB processes as compared to that by conventional inductively coupled plasma etching (ICP). (4) Recorded high I-ON/I-OFF ratio and low subthreshold swing (S.S. similar to 70 mV/dec.) of Ge n-FinFETs. (5) Excellent immunity for short channel effect of Ge FinFETs.
UWB Gilbert downconverter with lumped-distributed phase-inverter rat-race coupler based on Chebyshev band-broadening technique
(2011-07-21)
Wei, H. -J.
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Meng, C.
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Chang, C. -H.
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Huang, G. -W.
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電子工程學系及電子研究所
A broadband Gilbert downconverter with a miniature phase-inverter rat-race coupler is demonstrated using 0.35 mu m SiGe BiCMOS technology. By lumped-distributed and band-broadening techniques, a large shrinkage ratio with wide bandwidth of Chebyshev response can be simultaneously attained in the spiral-shape coplanar-stripline phase-inverter rat-race coupler. The area of the demonstrated lumped-distributed phase-inverter rat-race coupler is 0.65 x 0.65 mm(2) and the experimental bandwidth ranging from 2.5 to 12.5 GHz is large enough to cover the UWB bandwidth. As a result, a broadband Gilbert downconverter with the proposed coupler achieves a conversion gain of 11-12 dB, IP(1dB) of -11 dBm, IIP(3) of -1 dBm and noise figure of 16 dB from 3 to 11 GHz.