Browsing by Author "Huang, Guan-Sheng"

Now showing 1 - 3 of 3

A low power programmable PRBS generator and a clock multiplier unit for 10 Gbps serdes applications
(2006)
Chen, Wei-Zen
;
Huang, Guan-Sheng
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents the design of a low power programmable PRBS generator and a low noise clock multiplier unit (CMU) for 10 Gbps serdes applications. The PRBS generator is capable of producing 2(7)-1, 2(10)-1, 2(15)-1, 2(23)-1, and 2(31)-1 b test pattern according to ITU-T recommendations. High speed and low power operations of the PRBS generator are achieved by 16 paths parallel feedback techniques. The measured jitter of the CMU is only 3.56 ps(rms), and the data jitter at the PRBS output is mainly determined by the CMU. Implemented in a 0.18 mu m CMOS process, the power dissipation for PRBS generator is only 10.8 mW, and the CMU consumes about 87mW.
Bit error rate tester and pseudo random bit sequences generator thereof
(2006-06-22)
Chen, Wei-Zen
;
Huang, Guan-Sheng
A bit error rate tester and a pseudo random bit sequences (PRBS) generator thereof are provided. The bit error rate tester includes a transmitter PRBS generator, a master PRBS generator, a slave PRBS generator, a comparator, and a counting unit. The transmitter PRBS generator generates a parallel N-bit (N is an integer larger than 1) original PRBS, wherein an object to be tested receives the original PRBS and outputs a parallel N-bit code to be tested. The master and the slave PRBS generators generate a master and a slave parallel N-bit PRBS, respectively. The comparator receives, compares, and determines whether the code to be tested, the master and the slave PRBS are the same or not, and outputs a comparison result. The counting unit coupling to the comparator counts a number of bit errors based on the comparison result.
Low-Power Programmable Pseudorandom Word Generator and Clock Multiplier Unit for High-Speed SerDes Applications
(2008-07-01)
Chen, Wei-Zen
;
Huang, Guan-Sheng
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents the design of a low-power programmable pseudorandom word generator (PRWG) and a low-noise clock multiplier unit (CMU) for high-speed SerDes applications. The PRWG is capable of producing test patterns with sequence length of 2(7) - 1, 2(10) - 1, 2(15) - 1, 2(23) - 1, and 2(31) - 1 b according to CCITT recommendations, and the random word is 16-bit wide. High-speed and low-power operations of the PRWG are achieved by parallel feedback techniques. The measured jitter of the CMU is only 3.56 ps(rms), and the data jitter at the PRWG output is mainly determined by the CMU. Implemented in an 0.18-mu m CMOS process, the power dissipation for the PRWG is only 10.8 mW, and the CMU consumes about 87 mW from a 1.8-V supply. This PRWG can be used as a low-cost substitute for external parallel test pattern generators.