Browsing by Author "Huang, Guo-Wei"

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0.13-mu M CMOS Q-BAND LEVELED-LO SUBHARMONIC MIXER WITH INJECTION-LOCKED FREQUENCY-DIVIDER QUADRATURE GENERATOR
(2009-11-01)
Su, Jen-Yi
;
Meng, Chinchun
;
Wu, Po-Yi
;
Huang, Guo-Wei
;
電子工程學系及電子研究所
In this article, a 40-GHz subharmonic Gilbert down-conversion mixer with an accurate quadrature local oscillator (LO) input is demonstrated using a standard 0.13-mu m CMOS technology. The quadrature-output frequency divider is realized by injection-locked oscillators and is used at the LO port to replace conventional RC-CR polyphase filters at higher frequencies. Furthermore, the proper Marchand balun at all RF stage is suitable for the standard Si-based process to generate precisely balanced signals despite the substrate loss. The measured conversion gat In is 4 dB at 40 GHz. The IP(1dB) IIP(3) of - 7 dBm and 2 dBm, respectively, tire achieved. The measured 3-dB RF bandwidth is very broad and about 12-GHz bandwidth when the 10-MHz IF frequency is fixed. The die Size is about I mm X I mm. (C) 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 2663-2665, 2009; Published online in Wiley InterScience (www.interscience.wiley.com), DOI 10.1002/mop.24714
0.18 mu m SiGe BiCMOS Microwave/Millimeter-wave Dual-Mode Dual-Conversion Receiver Architecture With a Tunable RF Channel Selection at Low-Flicker-Noise Microwave Mode
(2017-01-01)
Chang, Wei Ling
;
Meng, Chinchun
;
Yang, Shih-Der
;
Huang, Guo-Wei
;
電機工程學系
A dual-mode receiver architecture with tens-MHz channel bandwidth at microwave mode and GHz channel bandwidth at millimeter-wave mode is demonstrated in this work with a tunable active filter for RF channel selection at microwave mode using 0.18 mu m SiGe BiCMOS technology. A dual conversion is employed to accommodate the wide-channel-bandwidth 60-GHz mode at the first conversion stage and the high-level-modulation 5-GHz mode is merged to the second conversion stage through sharing the 5-GHz switchable Gilbert IQ mixers with the 60-GHz mode. A tunable RF active filter is inserted between the 5-GHz LNA and the second stage mixer to serve as RF channel selection at the 5-GHz mode with the ability of relaxing the stringent linearity requirement imposed by high-level-modulation scheme. 10 dB gain with a 2-GHz channel bandwidth at the 60-GHz mode and 23 dB gain with a 20 MHz channel bandwidth within the 600 MHz tuning range at 5-GHz mode are demonstrated with a low-flicker-noise corner of less than 60 KHz at the 5-GHz mode because of the use of SiGe HBT as the IQ Gilbert mixer cores at the second conversion stage.
0.35-mu m SiGe BiCMOS Weaver Image Rejection Receiver with 60-GHz Double-Quadrature Sub-harmonic Schottky Diode Mixer and 10-GHz Double Quadrature Gilbert Mixer
(2017-01-01)
Wang, Kuo-An
;
Meng, ChinChun
;
Lo, Tai-Lin
;
Huang, Guo-Wei
;
電機工程學系
A Weaver image rejection receiver using 60-GHz double-quadrature sub-harmonic Schottky diode mixer is demonstrated using 0.35-pm SiGe BiCMOS technology. A miniature RF quadrature generator is realized to generate 60-GHz quadrature RE signals. A Weaver image rejection architecture is applied in this paper to filter out the image signals. A triple-balanced sub-harmonic Schottky diode mixer with a trifilar transformer is adopted to the first down conversion stage to obtain good LO1-RF and 2LO(1)-RE isolations while the down-converted IF1 signals are converted to the base band I/Q signals with a double-quadrature Gilbert mixer at the second down conversion stage. As a result, a 60-GHz Weaver image rejection receiver with a 2-GHz channel bandwidth is achieved with IP1dB of 2 dBm and HP3 of 14 dBm.
11.8 GHz GaInP/GaAs HBT dynamic frequency divider using HLO-FF technique
(2008-10-01)
Wei, Hung-Ju
;
Meng, Chinchun
;
Chang, YuWen
;
Huang, Guo-Wei
;
電信工程研究所
An integrated GaInP/GaAs heterojunction bipolar transistor (HBT) dynamic frequency divider based on HLO-FF (high-speed latching operating flip-flop) structure is demonstrated rot 4.1-11.8 GHz. In this experiment, et conventional static,frequency divider using the same cut-off-frequency device is also fabricated for comparison. By biasing the HBT transistors around the peak of f(T) and optimizing the I(read)/I(latch) tire maximum operating frequency of the HLO-FF is greatly improved date to higher slew-rate and smaller voltage swing. The speed of HLO-FF is faster about 48% than that of static structure. The core current is 13 mA cot the supply voltage of 5V. (C) 2005 Wiley Periodicals, Inc.
12 similar to 18 GHz Resistive Mixer with a Miniature Marchand Balun using Standard CMOS Process
(2009)
Wei, Hung-Ju
;
Meng, Chinchun
;
Tsung, Kuan-Chang
;
Huang, Guo-Wei
;
電信工程研究所
A 12 similar to 18 GHz fundamental resistive mixer is demonstrated using standard 0.13 mu m CMOS technology. A Marchand Balun directly on lossy silicon substrate is integrated with the resistive mixer to generate equal-amplitude and out-of-phase signal for LO pumping. The size of the Ku-band Marchand balun only occupies 478 mu m x 250 mu m due to higher silicon dielectric constant. The measured conversion loss of the resistive mixer is around 22 dB under f(IF)=3 GHz and P(LO)=6 dBm. The small required LO power reveals that the Marchand balun does not suffer serious loss from silicon substrate. The miniature technique makes passive components more compact and easier to be integrated with IC circuit design.
16-GHz mHEMT Double-Quadrature Gilbert Down-Conversion Mixer With Polyphase Filters
(2013)
Hsiao, Yu-Chih
;
Meng, Chinchun
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Su, Jen-Yi
;
Yu, Sheng-Wen
;
Huang, Guo-Wei
A 16-GHz double-quadrature very low IF down conversion mixer with polyphase filters is demonstrated using 0.15-nm metamorphic high electron mobility transistor (mHEMT) technology. Due to the hgih cut-off frequency of mHEMT device, the image rejection Gilbert mixer works at 16 GHz. The polyphase filters are employed to generate differential quadrature signals and eliminate the image signal at RF/LO stages and IF stage, respectively, in the double quarture configuration. When RF and LO frequencies are designed around 16 GHz and an IF frequency is 32 MHz, The double-quadrature Gilbert down-converter has 32-dB image rejection ratio, 1.7-dB conversion gain, -5-dBm IP1dB, and 5-dBm IIP3. The die size is 3.0 mm x 3.2 mm.
16.4 GHz SiGe BiCMOS Sub-Harmonic Mixer With Reactive I/Q Generators in RF and LO Paths
(2009)
Tseng, Sheng-Che
;
Syu, Jin-Siang
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Su, Jen-Yi
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Wei, Hung-Ju
;
Meng, Chinchun
This paper demonstrates a high-frequency 0.35-mu m SiGe BiCMOS sub-harmonic downconverter with reactive in-phase and quadrature-phase (I/Q) generators. Two reactive I/Q generators are integrated in our work to provide differential quadrature RI and LO signals. The I/Q sub-harmonic downconverter with single-ended LO, RI, and IF (IM) ports has a conversion gain of 1 dB, IP(1dB) of -10 dBm, IIP(3) of 0 dBm and IIP(2) of 21 dBm at 16.4 GHz. The magnitude and phase errors between the I and Q channels are 1.34% and 0.6 degrees, respectively. The dc power consumption of this I/Q mixer without output buffers is approximately 5 mW.
17-GHz pHEMT Gilbert Single-Quadrature Downconverter With Polyphase Filters for Image Rejection
(2010-01-01)
Wei, Hung-Ju
;
Meng, Chinchun
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Su, Jen-Yi
;
Yu, Sheng-Wen
;
Huang, Guo-Wei
A 17-GHz Gilbert single-quadrature down-converter (SQDC) with polyphase filters is successfully demonstrated using 0.15-mu m pseudomorphic high electron mobility transistor (pHEMT) technology for the first time to the best of our knowledge. Thanks to the semi-insulating GaAs substrate and an advanced technology, the image rejection Gilbert mixer works well at high frequencies. A polyphase filter at the LO stage is employed to generate precisely differential quadrature signals and a four-stage polyphase filter at the IF stage can filter out the unwanted image signal to achieve image rejection. From 10-MHz to 90-MHz IF frequencies, a 30-dB image rejection ratio is achieved when RF and LO frequencies are designed around 17 GHz. The Gilbert SQDC has a 5.5-dB conversion gain, 0-dBm IP1db, and 16-dBm IIP3.
2-GHz 1.35-dB NF pHEMT Single-Voltage-Supply Process-Independent Low-Noise Amplifier
(2018-01-01)
Syu, Jin-Siang
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Meng, Chinchun
;
Yang, Chun
;
Huang, Guo-Wei
;
電子工程學系及電子研究所
A 2-GHz single-voltage-supply 0.15-mu m depletion-mode (D-mode) pseudomorphic high electron-mobility transistor (pHEMT) low-noise amplifier (LNA) is demonstrated with a proposed process-independent self-biasing scheme. The current-reused technique is also employed to achieve a common-source common-drain two-stage LNA under a dc current of 10.85 mA at a 3-V supply. As a result, the proposed LNA achieves 20-dB power gain and 1.35-dB noise figure (NF) at 2 GHz while the minimum NF=1.3 dB occurs at 2.4 GHz.
.2.4 GHz divide-by-256 similar to 271 single-ended frequency divider in standard 0.35-mu m CMOS technology
(2005)
Tseng, Sheng-Che
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Meng, Chinchun
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Li, Shao-Yu
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Su, Jen-Yi
;
Huang, Guo-Wei
This paper demonstrates a low-cost 2.4 GHz single-ended frequency divider with the divide-by-value from 256 to 271 in standard 0.35-um 2P4M CMOS technology. This frequency divider is composed of a synchronous CML divide-by4/5 prescaler, an asynchronous TSPC TFF divide-by-64 divider and digital control circuitry. This proposed divider is single-ended and compatible to the single-ended low-phase-noise Colpitts VCO. The operating frequency range of the divider is from 400 MHz to 2.9 GHz. Most of input sensitivity levels are about -10 dBm and the lowest level is -25 dBm at 2.4 GHz. Its core power consumption is about 28 mW. The chip size is 1.20.7 mm(2).
2.4-GHz 7.4-mW 300-kHz Flicker-Noise-Corner Direct Conversion Receiver Using 0.18 mu m CMOS and Deep-N-Well NPN BJT
(2013)
Chang, Wei-Ling
;
Meng, Chin-Chun
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Syu, Jin-Siang
;
Wang, Chia-Ling
;
Huang, Guo-Wei
A low-power low-flicker-noise receiver is demonstrated using 0.18 mu m CMOS technology. Vertical-NPN bipolar junction transistors (BJTs) in standard CMOS process are used to substitute the mixer switching core and the input stage of subsequent IF VGA. Compared with the conventional CMOS mixer, the excellent flicker noise performance is obtained. As a result, the receiver achieves a 47 dB voltage gain at 2.4-GHz, and the noise figure is 9.6 dB at IF=100 kHz and 5.6 dB for IF>300 kHz. The total current consumption is 4.3 mA at 1.8 V supply voltage.
2.4-GHz Tunable Miniature CMOS Active Bandpass Filter With Two Transmission Zeros Using Lumped Stepped-Impedance Ring Resonator
(2018-01-01)
Hsiao, Yu-Chih
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Meng, Chinchun
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Chien, Hsieh-Hsiu Chang
;
Huang, Guo-Wei
;
電機工程學系
This paper demonstrates a small-size 2.4-GHz CMOS active bandpass filter with two transmission zeros using a lumped stepped-impedance ring resonator. To obtain low insertion loss and small size, four high-Q active inductors using 0.18 gm CMOS transistors only are employed in the design. The measured insertion loss is 2.9-dB at 2.4 GHz center frequency with two transmission zeros located at 2.1 GHz and 3.1 GHz, respectively. By tuning the bias currents of active inductors, the center frequency has 1.4 GHz tuning range and the 1-dB bandwidth can be adjusted in the range of 190 MHz to 260 MHz. The demonstrated active filter occupies a small chip area of 0.47 mm x 0.33 mm excluding I/O pads and has 24 dB noise figure. Thus, an active filter with a preceding two-stage common-source LNA for suppression of noise of the active filter is also demonstrated and the resulting LNA + active filter has 6 dB noise figure. The power consumption of the active filter core and the LNA core is 9 mW and 7.2 mW, respectively.
2.4/5.7-GHz Dual-Band Dual-Conversion Architecture With Correlated LO Signal Generators
(2009)
Syu, Jin-Siang
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Meng, Chinchun
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Yu, Sheng-Wen
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Wu, Tzung-Han
;
Huang, Guo-Wei
A 2.4/5.7-GHz dual-band dual-conversion downconverter is demonstrated using 0.35-mu m SiGe hetero-junction bipolar transistor (HBT) technology. This downconverter employs a complex dual-conversion system and a complex filter to reject the first and second image signals, respectively. The LO(1) frequency is 2.5 times the LO(2) frequency and is generated by a divide-by-two divider, a frequency doubler and a single-sideband up-converter. As a result, the correlated LO signals maintain excellent image-rejection performance of the dual-conversion system while only one LO input is needed. The downconverter achieves a 40/39-dB image-rejection ratio of the first image and a 44/46-dB image-rejection ratio of the second image for 2.4/5.7-GHz modes, respectively.
30-GHz mHEMT Divide-by-Three Injection-Locked Frequency Divider With Marchand Balun
(2015)
Chang, Wei-Ling
;
Meng, Chinchun
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Tsung, Kuan-Chang
;
Huang, Guo-Wei
;
電子工程學系及電子研究所
In this paper, the first fully integrated 0.15-mu m InAlAs/InGaAs metamorphic high electron mobility transistor (mHEMT) divide-by-three injection locked frequency divider (ILFD) with Marchand balun is demonstrated. The mHEMT technology has 110-GHz cutoff frequency and high tranconductance. Moreover, the Marchand Balun on the semi-insulating GaAs substrate has a low-loss property to provide broadband and balanced differential signals at millimeter wave frequencies. The divide-by-three ILFD performs the locking range from 28.8 GHz to 31.6 GHz under the supply voltage of 6 V and the core current consumption is 17.8 mA.
40-GHz CMOS Subharmonic Gilbert Mixer With Quadrature Injection-Locked Frequency Divider
(2008)
Su, Jen-Yi
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Meng, Chinchun
;
Wu, Po-Yi
;
Huang, Guo-Wei
;
電信工程研究所
5-6 GHz 9.4 mW CMOS Direct-Conversion Passive-Mixer Receiver With Low-Flicker-Noise Corner
(2012-01-01)
Hsiao, Yu-Chih
;
Meng, Chinchun
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Syu, Jin-Siang
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Lin, Chung-Yo
;
Wong, Shyh-Chyi
This paper demonstrates a low-power and low-flicker-noise direct-conversion receiver using double-balanced passive mixer. The deep-n-well vertical-NPN bipolar junction transistor is placed as at the input stage of the IF amplifier to reduce the flicker noise in the 0.18 um standard CMOS process. As a result, conversion gain achieves 50-dB gain when the LO power is 10 dBm and the noise figure is 7-dB at 100 kHz. The totally power consumption is 9.4 mW at 1.8 V voltage supply.
5-6 GHz CMOS Low-Noise Direct Conversion Receiver Using a Differential RF VGA with a Differential Inductor Load
(2016)
Chang, Wei-Ling
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Meng, Chinchun
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Chang, Chih-Kai
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Huang, Guo-Wei
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電子工程學系及電子研究所
A low-noise low-power direct conversion receiver with a differential RF VGA is demonstrated using 0.18um CMOS technology. A topology that uses a differential inductor load for a differential RF VGA is employed for the single-to-differential conversion. Since the common-mode rejection ratio of a differential variable gain amplifier is increased by the mutual magnetic coupling in a differential inductor load, this work achieves noise floor less than 5 dB covering the 5-6 GHz band. Moreover, the conversion gain is around 50 dB and the total current consumption is 4.75 mA at 1.8 V supply voltage.
5.2 Ghz high isolation sige BICMOS CMFB Gilbert mixer
(2007-02-01)
Meng, Chinchun
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Wu, Tzung-Han
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Wu, Tse-Hung
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Huang, Guo-Wei
;
電信工程研究所
Active PMOS loads with common mode feedback to stabilize the bias points are employed in the Gilbert mixer loads to increase the mixer gain. Good device matching and the deep trench isolation technique in the SiGe HBT technology can improve the port-to-port isolations. A 16 dB conversion gain, Ip(ldB) = -21 dBm and IIP3 = - 11 dBm using 0.35 mu m SiGe BiCMOS Gilbert downconversion micromixer is demonstrated when RF = 5.2 GHz and LO = 5.17 GHz with -66 dB LO-IF, -52 dB LO-RF, and -24 dB RF-IF isolations. (c) 2006 Wiley Periodicals, Inc.
5.8 GHz 4.7 mA Zero-IF Passive Mixer Receiver Using a Step-Down Transformer for Gain Enhancement
(2015)
Chang, Wei-Ling
;
Meng, Chinchun
;
Lin, Chung-Yo
;
Huang, Guo-Wei
;
電子工程學系及電子研究所
This paper demonstrates a 5.8 GHz low-power, low flicker -noise I/Q zero-IF receiver in 0.18-um CMOS process. Passive resistive mixers and deep-n-well vertical-NPN (V-NPN) bipolar junction transistors (BJTs) as the transconductance stage of the IF amplifier are employed to improve the flicker noise problem. The passive mixer is in current mode operation and thus a step-down transformer is used at the LNA output to enhance the current gain. By carefully designing the 4:2 stepdown transformer, the conversion gain of the whole zero-IF receiver performs up to 51 dB when LO power is 6 dBm, and the 3-dB bandwidth covers 5.7-6.1 GHz with the current consumption of 4.7 mA at 1.8 V supply. The flicker noise corner is 100 kHz and the noise floor is 6.5 dB. The I/Q amplitude mismatch and phase difference are below 0.05 dB and 2.5, respectively.
60-GHz 0.18-mu m CMOS Schottky-Diode Ring-Mixer Down-Converter
(2014)
Hsiao, Yu-Chih
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Meng, Chinchun
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Wang, Ta-Wei
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Huang, Guo-Wei
;
電機學院
A 60-GHz dual conversion down-converter based on n-type Silicon-based Schottky diodes has been demonstrated in the low-cost 0.18-mu m CMOS technology. Four Schottky diodes in the ring shape configuration with two Marchand Baluns are used for the RF mixer while a double-balanced resistive mixer is used as the second down-converted IF mixer. As a result, the 60-GHz dual-conversion down-converter has conversion gain around 6 dB and noise figure around 18 dB in the RF frequency range of 57 similar to 64 GHz. The total power consumption is 32.8 mW at 2.5 V.