Browsing by Author "Huang, HT"

Now showing 1 - 10 of 10

A physical model for hole direct tunneling current in P+ poly-gate PMOSFETs with ultrathin gate oxides
(2000-11-01)
Yang, KN
;
Huang, HT
;
Chang, MC
;
Chu, CM
;
Chen, YS
A model of the hole direct tunneling gate current accounting for heavy and light hole's subbands in the quantized inversion layer is built explicitly. This model comprises four key physical parameters: inversion layer charge density, hole impact frequency on SiO2/Si interface, WKB transmission probability, and reflection correction factor. With the effective hole mass m(oxh) = 0.5m(o) for parabolic dispersion relationship in the oxide, experimental reproduction without any parameter adjustment is consistently achieved in p(+) poly-gate pMOSFETs with 1.23, 1.85, and 2.16 nm gate oxide thicknesses. The proposed model can thereby serve as a promising characterization means of direct tunnel oxides. In particular, it is calculated that the secondary subbands and beyond, although occupying few holes, indeed contribute substantially to the direct tunneling conduction due to effective lo,vcr barrier heights, and are prevailing over the first subbands for reducing oxide field down below 1 MV/cm.
A trap generation closed-form statistical model for intrinsic oxide breakdown
(2001-06-01)
Huang, HT
;
Chen, MJ
;
Su, CW
;
Chen, JH
;
Hou, CS
A trap generation statistical model with the trap sphere radius r as parameter has been newly formulated in closed-form for intrinsic breakdown of ultrathin oxides and, by incorporating the trap filling fraction p as the secondary parameter, can be practically useful in a manufacturing process. Experimental reproduction for different oxide thicknesses and areas has been achieved through the model. A certain criterion has readily been drawn from the model, with which the ultimate thickness limit for breakdown can be set.
Back-gate bias enhanced band-to-band tunneling leakage in scaled MOSFET's
(1998-04-01)
Chen, MJ
;
Huang, HT
;
Hou, CS
;
Yang, KN
;
電子工程學系及電子研究所
The drain leakage current in MOSFET's in the present standard process is separated into three distinct components: the subthreshold conduction, the surface band-to-band tunneling (BTBT), and the bulk BTBT, Each of the three shows different dependencies on hack-gate bias, As a result, the hulk BTBT, increasing exponentially with increasing the magnitude of back-gate reverse bias, promptly dominates the drain leakage, Additional experiment highlights the effect of the increased hulk dopant concentrations as in next-generation scaled MOSFET's on the bulk BTBT, This sets the hulk BTBT a significant constraint to the low-voltage. low-power, high-density circuits employing the back-gate reverse bias, In the work, the measured drain leakage of interest is successfully reproduced by two-dimensional (2-D) device simulation.
Characterization and modeling of edge direct tunneling (EDT) leakage in ultrathin gate oxide MOSFETs
(2001-06-01)
Yang, KN
;
Huang, HT
;
Chen, MJ
;
Lin, YM
;
Yu, MC
This paper examines the edge direct tunneling (EDT) of electron from n(+) polysilicon to underlying n-type drain extension in off-state n-channel MOSFET's having ultrathin gate oxide thicknesses (1.4-2.4 mm), It is found that for thinner oxide thicknesses, electron EDT is more pronounced over the conventional gate-induced-drain-leakage (GIDL), bulk band-to-band tunneling (BTBT), and gate-to-substrate tunneling, and as a result, the induced gate and drain leakage is better measured per unit gate width. A physical model is for the first time derived for the oxide field fox at the gate edge by accounting for electron subband in the quantized accumulation polysilicon surface. This model relates fox to the gate-to-drain voltage, oxide thickness, and doping concentration of drain extension, Once fox is known, an existing DT model readily reproduces EDT I-V consistently and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to EDT is projected as well.
Edge hole direct tunneling in off-state ultrathin gate oxide p-channel MOSFETs
(2000)
Yang, KN
;
Huang, HT
;
Chen, MJ
;
Lin, YM
;
Yu, MC
This paper examines the edge direct tunneling (EDT) of hole from p(+) polysilicon to underlying p-type drain extension in off-state p-channel MOSFETs having ultrathin gate oxide thicknesses (1.2 - 2.2 nm). It is found that for thinner oxide thicknesses, hole EDT is more pronounced over the conventional GIDL and gate-to-channel tunneling, and as a result, the induced gate and drain leakage is better measured per unit gate width. A physical model accounting for heavy and light hole's subbands in the quantized accumulation polysilicon surface is built explicitly. This model consistently reproduces EDT I-V and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to EDT is projected as well.
Edge hole direct Tunneling leakage in ultrathin gate oxide p-channel MOSFETs
(2001-12-01)
Yang, KN
;
Huang, HT
;
Chen, MJ
;
Lin, YM
;
Yu, MC
This paper examines the edge direct tunneling (EDT) of holes from p(+) polysilicon to underlying p-type drain extensions in off-state p-channel MOSFETs having ultrathin gate oxides that are 1.2 nm-2.2 nm thick. It is for the first time found that for thinner oxides, hole EDT is more pronounced than both conventional gate-induced drain leakage (GIDL) and gate-to-channel tunneling. As a result, the induced gate and drain leakage is more accurately measured per unit gate width. Terminal currents versus input voltage are measured from a CMOS inverter with gate oxide thickness T-OX = 1.23 nm, exhibiting the impact of EDT in two standby modes. For the first time, a physical model is derived for the oxide field E-OX at the gate edge by accounting for the heavy and light holes' subbands in the quantized accumulation polysilicon surface. This model relates E-OX to the gate-to-drain voltage, oxide thickness, and doping concentration of the drain extension. Once E-OX is known, an existing direct tunneling (DT) model consistently reproduces EDT current-voltage (I-V), and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to hole EDT is projected.
Forward gated-diode measurement of filled traps in high-field stressed thin oxides
(2000-08-01)
Chen, MJ
;
Kang, TK
;
Huang, HT
;
Liu, CH
;
Chang, YJ
The forward gated-diode monitoring technique can find its potential applications in assessing the filled traps in MOSFET thin oxides, which are subjected to high-field stressing and then followed by hot-electrons filling scheme. Our measurement of the gate voltage shift associated with the forward current peak produces a power lan relation between the filled trap density and the electron stress fluence, indeed in close agreement with that obtained by MOSFET threshold voltage shift.
Monte Carlo sphere model for effective oxide thinning induced extrinsic breakdown
(2000-04-01)
Huang, HT
;
Chen, MJ
;
Chen, JH
;
Su, CW
;
Hou, CS
The Monte Carlo sphere model is extended to deal with the extrinsic time-dependent-dielectric-breakdown (TCDB) by incorporating the well-known "effective oxide thinning" concept. Percolation simulation, based on this model for the first time, evidences that the process defects induced extrinsic TDDB is also statistical in nature as is the intrinsic one, and is characterized by a probability function defining local oxide thinning. The experimental bimodal or even multimodal characteristics can be reproduced accordingly. Furthermore, the simulation results in the extrinsic regime are found to be sample-size (i.e., the total number of samples that span the breakdown statistics) dependent, suggesting that care should be taken when evaluating the extrinsic TDDB data in a real manufacturing process.
Separation of channel backscattering coefficients in nanoscale MOSFETs
(2004-09-01)
Chen, MJ
;
Huang, HT
;
Chou, YC
;
Chen, RT
;
Tseng, YT
Channel backscattering coefficients in the kBT layer (near the source) of 1.65-nm-thick gate oxide, 68-nm gate length bulk n-channel MOSFETs are systematically separated into two distinct components: the quasithermal-equilibrium mean-free-path for backscattering and the width of the kBT layer. Evidence to confirm the validity of the separation procedure is further produced: 1) the near-source channel conduction-band profile; 2) the existing value of kBT layer width from the sophisticated device simulation; and 3) an analytic temperature-dependent drain current model for the channel backscattering coefficients. The findings are also consistent with each other and therefore corroborate channel backscattering as the origin of the coefficients. Other interpretations and clarifications are determined with respect to the very recently released Monte Carlo particle simulation. Consequently, it can be reasonably claimed that the separated components, as well as their dependencies on temperature and bias, are adequate while being used to describe the operation of the devices undertaken within the framework of the channel backscattering theory.
Temperature dependent channel backscattering coefficients in nanoscale MOSFETs
(2002)
Chen, MJ
;
Huang, HT
;
Huang, KC
;
Chen, PN
;
Chang, CS
The ratio of the mean-free-path to the critical length near the low-field source is key to channel backscattering characteristics in nanoFETs. To extract it, we perform temperature experiment from -40 degreesC to 75 degreesC on 17 Angstrom thick gate oxide MOSFETs with varying mask gate lengths down to 75 nm. In this paper we report that once the saturation drain current is measured against temperature, the mean-free-path lambda with respect to the critical length l can readily be assessed at pecific temperature. Dependencies on gate length, drain voltage, and gate voltage are then established that further enable nanoFETs scaling projections. The temperature dependent version of existing backscattering model is derived in this work.