Browsing by Author "Huang, Han-Hsiang"

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A Constant-on-Time Control DC-DC Buck Converter With the Pseudowave Tracking Technique for Regulation Accuracy and Load Transient Enhancement
(2018-07-01)
Yang, Wen-Hau
;
Huang, Chao-Jen
;
Huang, Han-Hsiang
;
Lin, Wei-Ting
;
Chen, Ke-Horng
Constant-on-time (COT) control with an additional current feedback path in conventional buck converters can remove the need of large equivalent series resistance (ESR) at the output capacitor but it induces degraded output voltage regulation accuracy and slow transient response owing to opposite reaction between the output voltage and the additional current feedback information. Therefore, this paper proposes the pseudowave tracking (PWT) technique to reduce the load-dependent dc offset voltage of output load regulation while keeping the fast transient response similar to conventional COT buck converter with large ESR. The PWT technique further improves the transient response instantly by extending on-time and off-time periods during light-to-heavy and heavy-to-light load changes, respectively. The test chip fabricated in 28 nm CMOS process has demonstrated the improvement of offset voltage from 42 to 4 mV, while the transient response can be improved to 4 and 5 mu s with load changes from 0.3 to 1.7 A and vice versa, respectively.
Adaptive Window Control (AWC) Technique for Hysteresis DC-DC Buck Converters With Improved Light and Heavy Load Performance
(2009-05-01)
Huang, Han-Hsiang
;
Chen, Chi-Lin
;
Chen, Ke-Horng
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper presents a new adaptive window control (AWC) technique to adjust the hysteresis window to reduce the output ripple at heavy loads and keep the switching frequency higher than the acoustic frequency at light loads. Therefore, the driving capability and the power conversion efficiency of the hysteresis converter are improved at heavy loads. Besides, a new class AB current sensing circuit is also proposed to provide fast and accurate current sensing signal for achieving fast hysteresis window adjustment. Experimental results show that the proposed AWC technique not only reduces the output ripple smaller than 12 mV when load current is 800 mA to improve the power conversion efficiency but also keeps the switching frequency higher than acoustic frequency at light loads to avoid undesired noise.
Current Feedback Compensation (CFC) Technique for Adaptively Adjusting the Phase Margin in Capacitor-Free LDO Regulators
(2008-01-01)
Yang, Huan-Chien
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Huang, Han-Hsiang
;
Chen, Chi-Lin
;
Huang, Ming-Hsin
;
Chen, Ke-Homg
Current feedback compensation technique (CFC) can adaptively adjust the phase margin for achieving better transient response than that with variant phase margin at different load current conditions. Not only fast transient response is attained due to suitable phase margin but also the minimum load current limitation can be greatly reduced to about 50 mu A without sacrificing bandwidth at tight load current condition. Besides, CFC technique can have high PSRR bandwidth with compatible compensation capacitors compared to the Q-reduction technique [6]. The capacitor-free LDO regulator with CFC technique is fabricated by TSMC 0.35 mu m 2P4M CMOS process with small compensation capacitors 5pF and 1.5pF. Experimental results demonstrate that the minimum load can be reduced to 50 mu A and transient response time with adaptively phase margin control is smaller than 1 mu s.
Current Feedback Compensation (CFC) Technique for Adaptively Adjusting the Phase Margin in Capacitor-Free LDO Regulators
(2008-01-01)
Yang, Huan-Chien
;
Huang, Han-Hsiang
;
Chen, Chi-Lin
;
Huang, Ming-Hsin
;
Chen, Ke-Homg
Current feedback compensation technique (CFC) can adaptively adjust the phase margin for achieving better transient response than that with variant phase margin at different load current conditions. Not only fast transient response is attained due to suitable phase margin but also the minimum load current limitation can be greatly reduced to about 50 mu A without sacrificing bandwidth at tight load current condition. Besides, CFC technique can have high PSRR bandwidth with compatible compensation capacitors compared to the Q-reduction technique [6]. The capacitor-free LDO regulator with CFC technique is fabricated by TSMC 0.35 mu m 2P4M CMOS process with small compensation capacitors 5pF and 1.5pF. Experimental results demonstrate that the minimum load can be reduced to 50 mu A and transient response time with adaptively phase margin control is smaller than 1 mu s.
Current-Mode Synthetic Control (CSC) Technique for High Efficiency DC-DC Boost Converters Over a Wide Load Range
(2011)
Su, Yi-Ping
;
Chen, Yi-Chun
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Huang, Han-Hsiang
;
Lee, Yu-Huei
;
Yang, Yao-Yi
The proposed current-mode synthetic control (CSC) technique in the design of boost converters can improve the transient response time and maintain high conversion efficiency over a wide load range. The CSC technique has high accuracy similar to the current-mode control and doesn't need the slope compensation for simplicity. Besides, the transient response is also improved due to the current-mode hysteresis control. The load-dependent switching frequency at light loads results in high power conversion efficiency. Experimental results show that the output voltage ripple can be kept smaller than 50mV over a wide load current range from 0mA to 400mA with power conversion efficiency higher than 90% at load current of 10mA.
Fast Mode-Switching Technique in Hrbrid-Mode Operation
(2008)
Chen, Chi-Lin
;
Hsieh, Wei-Lun
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Huang, Han-Hsiang
;
Chen, Ke-Horng
;
電控工程研究所
A fast mode-switching technique between pulse width modulation (PWM) and pulse frequency modulation (PFM) modes Is proposed to keep high efficiency over wide load range. Load dependent zero-current detector (ZCD) can effectively speed up the transition from PWM to PFM mode. Especially, the overshoot voltage can be minimized by using the reversed current provided by the ZCD circuit. Furthermore, the undershoot voltage of the transition from PFM to PWM mode can be reduced because the recovery time can be reduced by restoring the output voltage of the error amplifier. Thus, the efficiency of current mode DC-DC buck converter is higher than 88% at light loads and the recovery time is smaller than 35 mu s when load current changes from 500mA to 10mA suddenly.
Minimized Right-Half Plane Zero Effect on Fast Boost DC-DC Converter Achieved by Adaptive Voltage Positioning Technique
(2010)
Liao, Jie-Yu
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Huang, Han-Hsiang
;
Chen, Ke-Horng
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電控工程研究所
;
Institute of Electrical and Control Engineering
The fast boost DC-DC converter designed with adaptive voltage positioning (AVP) technique to minimized the right-half plane zero effect is proposed. The concept of constant output impedance is a universal design principle in former works with AVP design. However, the right-half plane (RHP) zero appear in control to output transfer function of boost converter obstruct achievement of constant output impedance. The AC adjusting skill proposed in this paper illustrates how to obtain relative constant output impedance and accomplish the AVP characteristic in boost converter. The boost converter design with the AVP technique provides much faster response time and smaller voltage overshoots or undershoots during the load transient compared with any control scheme presented before. The simulation results is presented to show excellent performance of faster than 4 mu s response time and the 40mV voltage drop when the load current changes from 100mA to 400mA.
Solid-Duty-Control Technique for Alleviating the Right-Half-Plane Zero Effect in Continuous Conduction Mode Boost Converters
(2012-01-01)
Huang, Han-Hsiang
;
Chen, Chi-Lin
;
Wu, Dian-Rung
;
Chen, Ke-Horng
;
電控工程研究所
This paper proposes a solid-duty-control (SDC) technique for application in boost converters to maintain a constant duty value and reduce dip voltage during load transient periods. Fast transient response was also achieved because of the variable transient enhancement controller. The proposed SDC technique can provide a stable and regulated output for edge-lit light-emitting diode backlight systems. This converter was used in a 0.25-mu m CMOS process. Experimental results show that compared with a conventional design without a fast transient technique, the proposed approach yields about 30% and 80% improvement in undershoot voltage and recovery time, respectively, as load current changes from 50 to 250 mA.