Browsing by Author "Huang, JD"

Now showing 1 - 11 of 11

A variable partitioning algorithm of BDD for FPGA technology mapping
(1997-10-01)
Jiang, JH
;
Jou, JY
;
Huang, JD
;
Wei, JS
;
交大名義發表
Field Programmable Gate Arrays (FPGA's) are important devices for rapid system prototyping. Roth-Karp decomposition is one of the most popular decomposition techniques for Look-Up Table (LUT)-based FPGA technology mapping. In this paper, we propose a novel algorithm based on Binary Decision Diagrams (BDD's) for selecting good lambda set variables in Roth-Karp decomposition to minimize the number of consumed configurable logic blocks (CLB's) in FPGA's. The experimental results on a set of benchmarks show that our algorithm can produce much better results than the similar works of the previous approaches [1], [4].
ALTO: An iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping
(2000-08-01)
Huang, JD
;
Jou, JY
;
Shen, WZ
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we propose an iterative area/performance tradeoff algorithm for look-up table (LUT)-based held programmable gate array (FPGA) technology mapping. First, it finds an area-optimized, performance-considered initial network by a modified area optimization technique. Then, an iterative algorithm consisting of several resynthesizing techniques is applied to trade the area for the performance in the network gracefully. Experimental results show that this approach can efficiently provide a complete set of mapping solutions from the area-optimized one to the performance-optimize one for the given design. Furthermore, these two extreme solutions produced by our algorithm outperform the results provided by most existing algorithms. Therefore, our algorithm is very useful for the timing-driven, LUT-based FPGA synthesis.
An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping
(1996)
Huang, JD
;
Jou, JY
;
Shen, WZ
;
交大名義發表
;
電子工程學系及電子研究所
In this paper, we propose an iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping. First, it finds an area-optimized performance-considered initial network by a modified area optimization technique. Then, an iterative algorithm consisting of several resynthesizing techniques is applied to trade the area for the performance in the network gracefully. Experimental results show that this approach can provide a complete set of mapping solutions from the area-optimized one to the performance-optimize one for the given design. Furthermore, these two extreme solutions, the area-optimized one and the performance-optimized one, produced by our algorithm outperform the results of most existing algorithms. Therefore, our algorithm is very useful for the timing driven FPGA synthesis.
BDD based lambda set selection in Roth-Karp decomposition for LUT architecture
(1996)
Jiang, JH
;
Jou, JY
;
Huang, JD
;
Wei, JS
;
交大名義發表
Field Programmable Gate Arrays (FPGA's) are important devices for rapid system prototyping. Roth-Karp decomposition is one of the most popular decomposition techniques for Look-Up Table (LUT)-based FPGA technology mapping. In this paper, we propose a novel algorithm based on Binary Decision Diagrams (BDD's) for selecting good lambda set variables in Roth-Karp decomposition to minimize the number of consumed configurable logic blocks (CLB's) in FPGA's. The experimental results on a set of benchmarks show that our algorithm can produce much better results than those of the previous approach [1].
Compatible class encoding in hyper-function decomposition for FPGA synthesis
(1998)
Jiang, JHR
;
Jou, JY
;
Huang, JD
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Recently, functional decomposition has been adopted for LUT based FPGA technology mapping with good results. In this paper, we propose a novel method for functional multiple-output decomposition. We first address a compatible class encoding method to minimize the compatible classes in the image function. After the encoding algorithm is applied, the decomposability will be improved in the subsequent decomposition of the image function. The above encoding algorithm is then extended to encode multiple-output functions through the construction of a hyper-function. Common sub-expressions among these multiple-output functions can be extracted during the decomposition of the hyper-function. Therefore, we can handle the multiple-output decomposition in the same manner as the single-output decomposition. Experimental results show that our algorithms are very promising.
Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture
(1995)
Huang, JD
;
Joy, JY
;
Shen, WZ
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Formal compliance verification of interface protocols
(2005)
Yang, YC
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Huang, JD
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Yen, CC
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Shih, CH
;
Jou, JY
Verifying whether a building block conforms to certain interface protocol is one of the important steps while constructing an SoC However, most existing methods have their own limitations. Simulation-based methods have the false positive problem while formal property checking methods may suffer from memory explosion and excessive runtime. In this paper, we propose a novel branch-and-bound algorithm for interface protocol compliance verification. The properties of the interface protocol are specified as a specification FSM, and the interface logic is formally verified at the higher FSM level. Using the FSM for property specification is relatively systematic than using other proprietary property languages, which greatly reduces the possibility of incomplete property identification. And it is shown theoretically and experimentally that the proposed algorithm can finish in reasonable time complexity.
On circuit clustering for area/delay tradeoff under capacity and pin constraints
(1998-12-01)
Huang, JD
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Jou, JY
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Shen, WZ
;
Chuang, HH
;
電子工程學系及電子研究所
In this paper, we propose an iterative area/delay tradeoff algorithm to solve the circuit clustering problem under the capacity constraint. It first finds an initial delay-considered area-optimized clustering solution by a delay-oriented depth-first-search procedure. Then, an iterative procedure consisting of several reclustering techniques is applied to gradually trade the area for the performance. We then show that this algorithm can be easily extended to solve the clustering problem subject to both capacity and pin constraints. Experimental results show that our algorithm can provide a complete set of clustering solutions from the area-optimized one to the delay-optimized one for a given circuit. Furthermore, comparing to the existing delay-optimized algorithms, ours achieves almost the same performance but with much less area overhead. Therefore, this algorithm is very useful on solving the timing-driven circuit clustering problem.
Stimulus generation for interface protocol verification using the non-deterministic extended finite state machine model
(2005)
Shih, CH
;
Huang, JD
;
Jou, JY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Verifying if air integrated component is compliant with certain interface protocol is a big issue in component-based SOC designs. Massive constrained random simulation stimuli are becoming crucial to achieve a high verification quality. To further improve the quality, the stimulus biasing technique should be used to guide the simulation to hit design corners. In this paper we model the interface protocol with the non-deterministic extended finite state machine (NEFSM), and then propose an automatic stimulus generation approach based oil the NEFSM. This approach is capable of providing numerous biasing options. Experiment results demonstrate the high controllability scheme.
Unified functional decomposition via encoding for FPGA technology mapping
(2001-04-01)
Jiang, JH
;
Jou, JY
;
Huang, JD
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Functional decomposition has recently been adopted for look-up tabel (LUT)-based field-programmable gate array (FPGA) technology mapping with good results. In this paper we propose a novel method to unify functional single;output and multiple-output decomposition. We first address a compatible class encoding algorithm to minimize the number of compatible classes in the image function. After applying the encoding algorithm, we can therefore improve the decomposability in the subsequent decomposition of the; image function. The above encoding algorithm is then extended to encode multiple-output functions through the construction of a hyperfunction, Common subexpressions among these multiple-output functions can be extracted during the decomposition of the hyperfunction, Consequently, we can handle multiple-output decomposition in the same manner as single-output decomposition. Experimental results show that our algorithms are promising.
Verification on port connections
(2004)
Lee, GW
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Wang, CY
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Huang, JD
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Jou, JY
;
電子工程學系及電子研究所
In a system-on-a-chip (SOC) design, several to hundreds Of design blocks or intellectual properties (IPs) are integrated to form a complex function. Prior to verify the functionality of the integrated IPs, it is very important to ensure the correctness of the port connections among these IPs. This paper addresses the problem of verification on port connections while IPs are integrated into a larger block or a system, and presents a new connection model and the corresponding error model for port connections. An algorithm providing the mininium pattern set and a general verification flow used to verify port connections are also proposed.