Browsing by Author "Huang, Jyun-Siang"

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Fringing electric field effect on 65-nm-node fully depleted silicon-on-insulator devices
(2006-09-01)
Ma, Ming-Wen
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Chao, Tien-Sheng
;
Kao, Kuo-Hsing
;
Huang, Jyun-Siang
;
Lei, Tan-Fu
In this study, the fringing electric field effect on 65-nm-node technology fully depleted silicon-on-insulator (FD SOI) device is comprehensively examined. A new anomalous degradation in device on-state/off-state characteristics on a nanoscale metaloxide-semiconductor field-effect transistor (MOSFET) with high-kappa gate dielectrics is reported, the so-called fringing-induced barrier lowering (FIBL). This is due to the decrease in fringing electric field and increase in the gate dielectric thickness when gate dielectric permittivity increased. We observe that FIBL can be effectively suppressed using a stack gate dielectric structure. In addition, we also implement a high-kappa offset spacer to further improve the on-state driving current I-on to approximately 26% higher than that of a conventional silicon dioxide offset spacer and reduce the off-state leakage current I-off by about 34%. This benefit is due to the enhanced high vertical channel electric field obtained via the offset spacer using a high-kappa material as a spacer. This enhanced fringing electric field can markedly increase I-on/I-off current ratio and reduce subthreshold swing (S-factor) to improve MOSFET performance, which implies that gate-to-channel controllability can be improved markedly. This would play an important role beyond the 65-nm-node technology.
High-kappa material sidewall with source/drain-to-gate non-overlapped structure for low standby power applications
(2006-11-01)
Ma, Ming-Wen
;
Chao, Tien-Sheng
;
Kao, Kuo-Hsing
;
Huang, Jyun-Siang
;
Lei, Tan-Fu
In this paper, fully depleted silicon-on-insulator (SOI) devices with source/drain extension shifts and a high-kappa offset spacers were investigated in detail. The calculated results show that the source/drain extension shift can decrease off-state leakage current I-off significantly by utilizing the extra electron barrier height in the source/drain extension shift region to reduce standby power dissipation. However, the on-state driving current In is also sacrificed simultaneously. To overcome this drawback, a high-kappa offset spacer is used to increase the on-state driving current I-on effectively by enhancing the vertical fringing electric field which elevates the channel voltage drop and reduces series resistance.
Poly-Si Thin-Film Transistor Nonvolatile Memory Using Ge Nanocrystals as a Charge Trapping Layer Deposited by the Low-Pressure Chemical Vapor Deposition
(2009-03-01)
Kuo, Po-Yi
;
Chao, Tien-Sheng
;
Huang, Jyun-Siang
;
Lei, Tan-Fu
;
電子物理學系
We have successfully developed and fabricated a poly-Si thin-film transistor (poly-Si TFT) nonvolatile memory using Ge nanocrystals (Ge-NCs) as a charge trapping layer. Process compatibility and memory operation of the device were investigated. The Ge-NC trapping layer was directly deposited by low-pressure chemical vapor deposition at 370 degrees C. Results show that the new poly-Si TFT nonvolatile Ge-NC memory has good programming/erasing efficiency, long charge retention time, and good endurance characteristics. These results show that poly-Si TFT nonvolatile Ge-NC memory is the promising nonvolatile memory candidate for system-on-panel application in the future.