Browsing by Author "Huang, Kun-Hua"

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An Efficient Hierarchical Banking Structure for Algorithmic Multiported Memory on FPGA
(2017-10-01)
Lai, Bo-Cheng Charles
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Huang, Kun-Hua
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Algorithmic multiported memory supports concurrent accesses by cooperating block RAMs (BRAMs) with algorithmic operations, and demonstrates the better performance per resource usage on FPGA when compared with register-based designs. However, the current approaches still use significant amount of FPGA resources and pose great design challenges when increasing the access ports. This paper proposes HB-NTX with a resource efficient hierarchical banking structure for nontable-based multi-ported memory design on FPGA. The regular design style enables a systematic flow to scale both read and write ports. When compared with the previous approaches, HB-NTX can reduce 62.03% BRAMs when composing a 2R4W memory with 32K depth. This paper further extends the HB-NTX to alleviate the complexity of the table-based memory designs. When compared with the previous table-based TBLVT approach, the proposed design for a 2R4W memory with 8K depth attains the cost reduction of 39.9%, 14.3%, and 15.6%, for registers, lookup tables, and BRAMs, respectively.
Scalable Mutli-Layer Barrier Synchronization on NoC
(2016)
Tseng, Yu-Lun
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Huang, Kun-Hua
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Lai, Bo-Cheng Charles
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電機學院
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電子工程學系及電子研究所
Barrier is a widely used synchronization mechanism adopted in different scales of parallel systems. Being a global operation in a system, scalability has become a critical design concern of the barrier implementation. Reducing the number of messages and hop count are main challenges for attaining a well-scalable barrier design. This paper proposes an efficient control mechanism and communication scheme for barrier operations and exploits novel multi-layer barrier algorithms on NoC (Network on Chip) based multiprocessor systems. A novel barrier controller and communication unit are introduced to enable efficient barrier synchronization on NoC. The proposed modules improve the cooperative communication between synchronization messages, and can be easily integrated into a general NoC switch. For a 32x32 network, the proposed 2-layer barrier can respectively reduce the latency and hop count up to 61.7% and 99.3%. The experimental results have also revealed in-depth analysis of different design options.