Browsing by Author "Huang, Li-Da"

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A Stochastic-Based Efficient Critical Area Extractor on Open Access Platform
(2009-01-01)
Chen, Bo-Zhou
;
Chen, Hung-Ming
;
Huang, Li-Da
;
Pan, Po-Cheng
;
電子工程學系及電子研究所
Due to inefficient calculation in current critical area analyzer, in this work we present a method of extracting critical area for short faults from the mask layout of an integrated circuit. The method is based on the concept of sampling framework and the geometry computation of critical area. By constructing the density table of layout, our weighted sampling approach can be more efficient, thus more suitable for the larger layout. The algorithm has been implemented on OpenAccess platform to allow efficient extraction of the critical area from an arbitrary mask layout. The results show that this method can reduce computation cost, and can still maintain the accuracy at the same time.
A Stochastic-Based Efficient Critical Area Extractor on Open Access Platform
(2009-01-01)
Chen, Bo-Zhou
;
Chen, Hung-Ming
;
Huang, Li-Da
;
Pan, Po-Cheng
;
電子工程學系及電子研究所
Due to inefficient calculation in current critical area analyzer, in this work we present a method of extracting critical area for short faults from the mask layout of an integrated circuit. The method is based on the concept of sampling framework and the geometry computation of critical area. By constructing the density table of layout, our weighted sampling approach can be more efficient, thus more suitable for the larger layout. The algorithm has been implemented on OpenAccess platform to allow efficient extraction of the critical area from an arbitrary mask layout. The results show that this method can reduce computation cost, and can still maintain the accuracy at the same time.
Using power gating techniques in area-array SoC floorplan design
(2007-01-01)
Yeh, Chi-Yi
;
Chen, Hung-Ming
;
Huang, Li-Da
;
Wei, Wei-Ting
;
Lu, Chao-Hung
Low power demand drives the development of lower power design architectures, among which power gating is one of the state-of-the-art techniques to achieve low power. NITCMOS (or sleep transistor) is applied when some of the blocks can be switched off without leakage power dissipation. This technique is widely used in circuit level design, but hardly used in higher level design stage. Due to early planning in power delivery for area-array design style, it is necessary to consider the power gating techniques in early SoC physical design stage. This paper presents a framework to insert coarse grain MTCMOS in SoC floorplanning stage, saving mainly leakage power. This work decides which modules have chance to save power by sleep transistors insertion, and reserves enough area for them during floorplarming. The results show that our approach works well and can obtain lower power floorplans with supply noise aware sleep transistor insertion in area-array architecture.