Browsing by Author "Huang, Ming-Hsiang"

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Bandwidth and Latency Aware Contribution Estimation in P2P Streaming System
(2014-09-01)
Ho, Cheng-Yun
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Huang, Ming-Hsiang
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Ho, Cheng-Yuan
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Tseng, Chien-Chao
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交大名義發表
In this article, a bandwidth and latency aware contribution estimation (BLACE) mechanism is proposed to enhance the efficiency of content distribution in a mesh peer-to-peer (P2P) streaming system. This is because the mesh P2P streaming system outperforms others in many aspects, but most content distribution mechanisms use only one of upload bandwidth and link latency as a factor, several contribution-aware schemes (CASs) just punish selfish peers, and some CASs only rearrange the content receiving order. Hence, the BLACE proposes a prevention way considering every peer\'s upload bandwidth, link latency, and the maximum playing delay of a stream at the same time to prioritize the content distribution. Moreover, BLACE is implemented on Coolstreaming with NS2 and experimental results show that BLACE could at the most shorten the receiving time about 15.44%, 13.94%, and 8.26%, and improve the whole performance about 7.05%, 2.81%, and 2.69% at the most, when it compares with the Coolstreaming, the Coolstreaming with bandwidth preference, and the Coolstreaming with latency preference, respectively.
On the And-Or-Scheduling Problems
(2014)
Yang, Wuu
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Huang, Ming-Hsiang
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Lee, Jenq-Kuen
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資訊工程學系
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Department of Computer Science
In the and-or scheduling model, a project consists of several tasks. Each task has a duration attribute. A task can be performed only when all of its requirements are satisfied. After a task is completed, more requirements become satisfied. A characteristic of the AOscheduling projects is that a requirement may be satisfied in several ways. Several questions concerning AOscheduling might be interesting, including whether the project can be completed, the earliest time a project can be completed, the minimal number of processors needed to complete the project, and assigning tasks to processors, etc. We use Petri nets and segment graphs to analyze AOscheduling projects.
Partial Flattening: A Compilation Technique for Irregular Nested Parallelism on GPGPUs
(2016)
Huang, Ming-Hsiang
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Yang, Wuu
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交大名義發表
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National Chiao Tung University
Supporting irregular nested parallelism on modern GPUs requires much effort. One should distribute the parallel tasks evenly while preserving reasonable memory usage. Moreover, the task distribution should also fit the thread hierarchy of the underlying GPU to fully exploit its computing power. We propose partial flattening, an automatic code transformation which translates annotated C programs to CUDA kernels. Thread blocks are treated as flat SIMT processors. Iterations are dynamically organized into batches. Batches are executed in a sequential (depth-first) order. A kernel is treated as multiple independent SIMT processors with an additional task-stealing mechanism. Partial flattening allows easy expression of nested parallelism and synchronization by annotating nested parallel loops or parallel-recursive calls, while preserving reasonable memory usage by the depth-first execution order. Our 2-level task distribution scheme does not need special hardware support, and fits well with the CUDA thread hierarchy. Experiments show that partial flattening outperforms NESL significantly in most benchmarks, and obtains 2.15x and 67x speedup over CUDA dynamic parallelism in Quicksort and the Bron-Kerbosch algorithm, respectively.