Browsing by Author "Huang, Ning-Chi"

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Analysis and Optimization of Variable-Latency Designs in the Presence of Timing Variability
(2017-01-01)
Tsai, Chang-Lin
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Cheng, Chao-Wei
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Huang, Ning-Chi
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Wu, Kai-Chiang
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資訊工程學系
Circuit performance has been the key design constraint for over a decade. Variable-latency design (VLD) paradigm was proposed for optimizing the overall performance in terms of throughput. In addition, process variations and aging effects manifest themselves as gate delay shifts, and in turn cause variability of circuit timing (timing variability). Required for dealing with the impact of timing variability better, detailed evaluation and analysis of circuit timing for VIM are actually not straightforward. In this paper, we present a systematic methodology for analyzing a VLD circuit, and identifying critical 1-cycle and 2-cycle paths/gates. Based on the criticality analysis, a gate sizing framework using particle swarm optimization (PSO) is proposed. Our objective is, in a less pessimistic fashion, making constructed VLD circuits better (less vulnerable to timing variability). The proposed framework is experimentally verified to be runtime-efficient and able to provide promising results. On average, an extra timing margin of 11% can be obtained without lengthening the clock period, and only 4% area overhead is introduced.
Exploration and Exploitation of Dual Timing Margins for Improving Power Efficiency of Variable-Latency Designs
(2019-01-01)
Huang, Ning-Chi
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Chen, Yu-Guang
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Wu, Kai-Chiang
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資訊工程學系
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Department of Computer Science
Circuit performance has been the key design constraint for over a decade. Variable-latency design (VLD) paradigm was proposed for optimizing the overall performance in terms of throughput. In addition, process variations and aging effects manifest themselves as gate delay shifts, and in turn cause variability of circuit timing (timing variability). Besides, Power consumption is another important design consideration. To deal with the impact of timing variability and power issue better, in this paper, we present a VDD assignment framework based on genetic algorithm (GA) to minimize the power consumption of VLD. Our objective is making constructed VLD circuits more power-efficient under given tolerance to timing variability. Experimental results show that on average our methodology can achieve 24% dynamic power reduction, while preserving at least 8% timing margin, with only 5% overhead in circuit area and leakage power.
Sensor-Based Approximate Adder Design for Accelerating Error-Tolerant and Deep-Learning Applications
(2019-01-01)
Huang, Ning-Chi
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Chen, Szu-Ying
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Wu, Kai-Chiang
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資訊工程學系
;
Department of Computer Science
Approximate computing is an emerging strategy which trades computational accuracy for computational cost in terms of performance, energy, and/or area. In this paper, we propose a novel sensor-based approximate adder for high-performance energy-efficient arithmetic computation, while considering the accuracy requirement of error-tolerant applications. This is the first work using in-situ sensors for approximate adder design, based on monitoring online transition activity on the carry chain and speculating on carry propagation/truncation. On top of a fully-optimized ripple-carry adder, the performance of our adder is enhanced by 2.17X. When applied in error-tolerant applications such as image processing and handwritten digit recognition, our approximate adder leads to very promising quality of results compared to the case when an accurate adder is used.