Browsing by Author "Huang, PR"

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Design of a 0.25-mu m CMOS 5.25GHz transceiver front-end
(2003)
Jou, CF
;
Huang, PR
;
Cheng, KH
;
電信工程研究所
;
Institute of Communications Engineering
This paper describes the design consideration and simulation performance for a fully integrated CMOS RF front-end for 5.25 GHz application. The single chip front-end circuit consists: a 2.65dB insertion loss transmit/receive switch (T/R switch), a 13dB power gain, 2.9dB NF low noise amplifier (LNA), and a 15dBm Pout-1dB power amplifier (PA). The IC has fabricated in a TSMC 0.25-mum CMOS technology. To achieve single chip design target, this chip was designed without any off-chip matching component. The front-end circuit was designed for two operation modes: transmission mode (TX) and receiving mode (RX). We can switch two operation modes by changing the control voltage of the T/R switch. The simulation results of the TX mode has the power gain 7.27 dB and the Pout-1dB is 12 dBm. The RX mode power gain is 9.64 dB and the IIP3 is 1.1 dBm.
Design of a fully integrated high linearity dual-band CMOS LNA
(2003)
Jou, CF
;
Cheng, KH
;
Huang, PR
;
Chen, MC
;
電信工程研究所
A fully-integrated dual-band LNA (Low Noise Amplifier) with high linearity is presented in this thesis. Designed and implemented in 0.25 mu m mixed-signal CMOS process, the LNA simultaneously delivered narrow-bans gain and matching at 2.45GHz and 5.25GHz. The LNA exhibits input matching with S-11 of -20.48dB at 2.45GHz and -16.6dB at 5.25GHz. And it achieves small-signal gain of 5.78dB and 3.24dB, noise figure 4.7dB and 5.69dB, and IIP3 7dBm and 17dBm.