Browsing by Author "Huang, Pei-Shu"

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An Efficient Thermal Estimation Scheme for Microprocessors
(2014-01-01)
Huang, Pei-Shu
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Chen, Quan-Chung
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Huang, Chen-Wei
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Tsao, Shiao-Li
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資訊工程學系
In recent years, thermal management, which improves the reliability, performance, power leakage, etc. of modern microprocessors, has been the subject of numerous computer architecture and system software studies. To determine the detailed thermal distribution of a microprocessor is among the critical tasks for thermal management. However, because thermal modeling tools require considerable computation time and memory to simulate fine-grain thermal information, they may be unsuitable for dynamic thermal management and hardware implementation. This study proposes a novel model based on reduced resistance-capacitance (RC) networks for efficiently calculating the temperature of a microprocessor. The proposed model is compared with two existing thermal simulation tools, namely, HotSpot [1] and Temptor [2]. The experiment studies show that the results generated using the proposed model differ from those of the existing tools by only 0.5 to 1.5%. However, the suggested model can increase computation speeds by 5 to 9 times and 98 to 161 times that of Temptor and HotSpot, respectively. For the memory usage, the proposed model consumes merely 0.45% of the space used by the existing tools.
High-Level Energy Consumption Model of Embedded Graphic Processors
(2015)
Huang, Chen-Wei
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Chung, Yu-An
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Huang, Pei-Shu
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Tsao, Shiao-Li
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資訊工程學系
Embedded graphic processing unit (GPU) is an indispensable component in enabling real-time rendering and graphic applications on mobile devices. However, embedded GPU consumes a considerable energy [1] which is critical for battery-operated devices. To understand the energy consumption of a graphic application, conventional approaches suggested the energy model based on hardware performance counters. However, those low-level energy models are mainly derived from GPUs of desktop computers, and they cannot be applied to embedded GPUs directly and the low-level models are less intuitive from a programmer\'s point of view. In this study, we consider a high-level energy consumption model for embedded graphic processors, and then we can estimate energy consumption of a graphic application based on graphic attributes of a scene. We conduct a number of experiments on real platforms to validate the proposed model. Our experimental results demonstrate that an average energy estimation error rate of 7.30% can be achieved.
Improving the Accuracy of the Leakage Power Estimation of Embedded CPUs
(2017-01-01)
Chin, Ting-Wu
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Tsao, Shiao-Li
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Hung, Kuo-Wei
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Huang, Pei-Shu
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資訊工程學系
Previous studies have used on-chip thermal sensors (diodes) to estimate the leakage power of a CPU. However, an embedded CPU equips only a few thermal sensors and may suffer from considerable spatial temperature variances across the CPU core, and leakage power estimation based on insufficient temperature information introduces errors. According to our experiments, the conventional leakage power models may have up to 22.9% estimation error for a 70-nm embedded CPU. In this study, we first evaluated the accuracy of leakage power estimates based on thermal sensors on different locations of a CPU and suggested locations that can reduce the error to 0.9%. Then, we proposed temperature-referred and counter-tracked estimation (TRACE) that relies on temperature sensors and hardware activity counters to estimate leakage power. The simulation results demonstrated that employing TRACE could reduce the error to 3.4%. Experiments were also conducted on a real platform to verify our findings.
Improving the Detection o Sequential Anomalies Associated with a Loop
(2019-01-01)
Fahmi, Faisal
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Huang, Pei-Shu
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Wang, Feng-Jian
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資訊工程學系
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電機資訊國際碩士學位學程
Workflow models are widely applied in business software design. A workflow model contains a set of systematic ordered tasks to achieve designated business goal(s) under the designed flow control. Analyzing artifact usage during design phase can prevent unexpected artifact result due to abnormal artifact operation(s). A sequential anomaly indicates a pair of activities operating on the same artifact that can result in redundant write or missing production. On the other hand, the iteration of a loop structure in a workflow cannot be statically analyzed, thus, detecting process of artifact anomalies in a loop is costly. In this paper, we present an effective method to detect all anomalies associated with a loop by removing the redundant computation due to the repeated structure of the body and control in the iterations. After the removing, the anomalies can be detected on a single iteration generated instead. Here, the process of anomaly detection is now simplified into two phases: First, a workflow model is transformed into a corresponding C-tree structure and next, the proposed anomaly detection methodology is applied to the C-tree. Compared with current approaches, our method can reduce the space complexity and decrease the execution times of anomaly detection as linear.