Browsing by Author "Huang, Po-Tsang"

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0.339fJ/bit/search Energy-Efficient TCAM Macro Design in 40nm LP CMOS
(2014)
Huang, Po-Tsang
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Lai, Shu-Lin
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Chuang, Ching-Te
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Hwang, Wei
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Huang, Jason
In this paper, a 256x40 energy-efficient ternary content addressable memory (TCAM) macro is designed and implemented in 40nm low power (LP) CMOS. Due to the thicker gate oxide in LP process, a 16T TCAM cell with p-type comparison circuits is proposed to increase the I-on/I-off difference of the dynamic circuitry. To further improve energy efficiency, don\'t-care-based ripple search-lines/bit-lines are used to reduce both the switching activities and wire capacitance. Moreover, column-based data-aware power control is employed for leakage power reduction and write-ability improvements. The experimental results show a leakage power reduction of 28.9%, a search-line power reduction of 31.74% and an energy efficiency metric of the TCAM macro of 0.339 fJ/bit/search.
0.4V Reconfigurable Near-Threshold TCAM in 28nm High-k Metal-Gate CMOS Process
(2018-01-01)
Chan, Yun-Sheng
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Huang, Po-Tsang
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Wu, Shang-Lin
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Lung, Sheng-Chi
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Wang, Wei-Chang
This paper presents a near-threshold configurable ternary content addressable memory (TCAM) design for energy-constrained neural network or software-defined network (SDN) applications. A TCAM architecture based on foundry-based 6T SRAM mini-array improves area efficiency and minimizes disturbs to enable operation down to 0.4V, and provides configurable lookup tables for users. To minimize dynamic power consumption, hierarchical precharge structure (HPRE) and don't-care based ripple search-line scheme are utilized for decreasing both the switching activities and wire capacitance. Moreover, power-gating technique, self-timed control and V-trip-tracking write-assist are used to reduce standby power, speed-up propagation delays of global signals and improve write-ability at low voltage, respectively. A reconfigurable TCAM is implemented using UMC 28nm high-k metal gate (HKMG) CMOS process. The design achieves operating frequency of 240MHz (20MHz) with energy consumption of 1.146 (0.621) fJ/bit/search at 0.9V (0.4V).
2-l.evel FIFO architecture design for switch fabrics in network-on-chip
(2006)
Huang, Po-Tsang
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Hwang, Wei
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The network-on-chip (NoC) architecture provides the integrated solution for system-on-chip (SoC) design. The buffer architecture and sizes, however, dominate the performance of NoC and influence on the design of arbiters in the switch fabrics. The 2-level FIFO architecture is proposed. It simplifies the design of the arbitration algorithm and gets better performance than other buffer architectures without increasing the buffer sizes. The concept of the shared memory mechanism and multiple accesses for the buffers are developed. The FIFO architecture is implemented and simulated with TSMC 0.13um CMOS technology by HSPICE and Verilog. The operation frequency of the 2-level FIFO reaches 400MHz.
2.5D Heterogeneously Integrated Bio-Sensing Microsystem for Multi-Channel Neural-Sensing Applications
(2014-01-01)
Huang, Po-Tsang
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Chou, Lei-Chun
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Huang, Teng-Chieh
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Wu, Shang-Lin
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Wang, Tang-Shuan
2.5D Heterogeneously Integrated Microsystem for High-Density Neural Sensing Applications
(2014-12-01)
Huang, Po-Tsang
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Wu, Shang-Lin
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Huang, Yu-Chieh
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Chou, Lei-Chun
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Huang, Teng-Chieh
Heterogeneously integrated and miniaturized neural sensing microsystems are crucial for brain function investigation. In this paper, a 2.5D heterogeneously integrated bio-sensing microsystem with mu-probes and embedded through-silicon-via (TSVs) is presented for high-density neural sensing applications. This microsystem is composed of mu-probes with embedded TSVs, 4 dies and a silicon interposer. For capturing 16-channel neural signals, a 24 x 24 mu-probe array with embedded TSVs is fabricated on a 5 x 5 mm2 chip and bonded on the back side of the interposer. Thus, each channel contains 6 x 6 mu-probes with embedded TSVs. Additionally, the 4 dies are bonded on the front side of the interposer and designed for biopotential acquisition, feature extraction and classification via low-power analog front-end (AFE) circuits, area-power-efficient analog-to-digital converters (ADCs), configurable discrete wavelet transforms (DWTs), filters, and a MCU. An on-interposer bus (mu-SPI) is designed for transferring data on the interposer. Finally, the successful in-vivo test demonstrated the proposed 2.5D heterogeneously integrated bio-sensing microsystem. The overall power of this microsystem is only 676.3 mu W for 16-channel neural sensing.
28nm Near/Sub-Threshold Dual-Port FIFO Memory for Shared Queues in Multi-Sensor Applications
(2018-01-01)
Wu, Yi-Chun
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Huang, Po-Tsang
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Wu, Shang-Lin
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Lung, Sheng-Chi
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Wang, Wei-Chang
For an energy-limited multi-sensing platform, ultra-low-power queueing design is one of the critical challenge to store low-speed sensing data with various sampling frequencies. In this paper, a near/sub-threshold dual-port first-in-first-out (FIFO) memory is proposed for shared queues in a unified queuing architecture. This ultra-lowpower FIFO memory is designed and implemented using bitinterleaved 12T near-/sub-threshold dual-port SRAM bit-cells, write/read-assist circuitries, and adaptive timing tracking circuits. The 12T bit-cell eliminates both read and write half-select disturbance. Additionally, an adaptive timing tracing circuitry and negative bit-line circuits are employed to against PVT variation and to enhance write ability, respectively. Furthermore, the self-timed pointers and short ripple bit-lines are designed to avoid global long metal lines with large loading. A 256x16 dual-port FIFO memory is implemented in UMC 28nm HKMG CMOS technology. This FIFO memory can be operated at 0.4V with 10MHz for read operations. Moreover, up to 60% power reduction can be achieved based on the proposed design techniques.
28nm Ultra-Low Power Near-/Sub- threshold First-In-First-Out (FIFO) Memory for Multi-Bio-Signal Sensing Platforms
(2016)
Hsu, Wei-Shen
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Huang, Po-Tsang
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Wu, Shang-Lin
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Chuang, Ching-Te
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Hwang, Wei
In this paper, an ultra-low-power near-/sub-threshold first-in-firstout (FIFO) memory is proposed for energy-constrained bio-signal sensing applications. This FIFO memory is designed and implemented using folded bit-interleaved 10T near-/sub-threshold SRAM bit-cells, self-timed pointers and bank-level power control circuits. The 10T SRAM cell is proposed for the bit-interleaving structure with 2.4X write static noise margin (SNM) improvement. The folded bit-interleaving structure reduces the bit-line capacitance and avoids long routing wires for the circular self-timed pointers. Additionally, the event-driven self-timed pointers are designed to reduce the power consumption of clock buffers. For further decreasing the overall power dissipation, bank-level column-based power control circuitry is proposed to switch the voltages for different banks to achieve 60.5% power saving. A 512x16 FIFO memory is implemented in UMC 28nm HKMG CMOS technology. Compared with the prior arts, 47X power reduction and 2.7X area efficiency can be achieved by the proposed design techniques.
A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist
(2017-07-01)
Wu, Shang-Lin
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Li, Kuang-Yu
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Huang, Po-Tsang
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Hwang, Wei
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Tu, Ming-Hsien
This paper presents a 28-nm 256-kb 6T static random access memory operating down to near-threshold regime. The cell array is built on foundry 4-by-2 mini-array with split single-ended large signal sensing to enable an ultra-short local bit-line of 4-b length to improve variation tolerance and performance, and to reduce disturb while maintaining manufacturability. The design employs threshold power gating to facilitate lower NAP (Sleep) mode voltage/power and faster wake-up for the cell array, and low-swing global read bit-line (GRBL) with integrated low-swing voltage precharger to improve read performance and reduce the dynamic read power. A cell Vtrip-tracking write-assist (VTWA) lowers the selected sub-array supply to cell inverter trip voltage to enhance write-ability while providing PVT tracking capability to ensure adequate data retention margin for unselected cells in the selected sub-array. The 256-kb test chip is implemented in UMC 28-nm high-kappa metal-gate (H kappa MG) CMOS technology with macro area of 1058.22 x 374.76 mu m(2). Error-free full functionality is achieved from 0.9 down to 0.5 V (limited by read VMIN) without redundancy. The low-swing GRBL reduces dynamic power by 6.5% (8.0%) at 0.9 V (0.6 V). The VTWA improves the write VMIN by 75 mV (from 0.525 to 0.45 V). The measured maximum operation frequency is 735 MHz (20 MHz) at 0.9 V (0.5 V), TT corner, 25(omicron).
A 16-Gb/s 14.7-mW Tri-Band Cognitive Serial Link Transmitter With Forwarded Clock to Enable PAM-16/256-QAM and Channel Response Detection
(2017-04-01)
Du, Yuan
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Cho, Wei-Han
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Huang, Po-Tsang
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Li, Yilei
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Wong, Chien-Heng
A cognitive tri-band transmitter (TX) with a forwarded clock using multiband signaling and high-order digital signal modulations is presented for serial link applications. The TX features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level at the receiver side, and then adapting modulation scheme, data bandwidth, and carrier frequencies accordingly based on detected channel information. The supported modulation scheme ranges from nonreturn to zero/Quadrature phase shift keying (QPSK) to Pulse-amplitude modulation (PAM) 16/256-Quadrature amplitude modulation(QAM). The proposed highly reconfigurable TX is capable of dealing with low-cost serial channels, such as low-cost connectors, cables, or multidrop buses with deep and narrow notches in the frequency domain (e.g., a 40-dB loss at notches). The adaptive multiband scheme mitigates equalization requirements and enhances the energy efficiency by avoiding frequency notches and utilizing the maximum available signal-to-noise ratio and channel bandwidth. The implemented TX prototype consumes a 14.7-mW power and occupies 0.016 mm(2) in a 28-nm CMOS. It achieves a maximum data rate of 16 Gb/s with forwarded clock through one differential pair and the most energy efficient figure of merit of 20.4 mu W/Gb/s/dB, which is calculated based on power consumption of transmitting per gigabits per second data and simultaneously overcoming per decibel worst case channel loss within the Nyquist frequency.
A 16Gb/s 14.7mW Tri-Band Cognitive Serial Link Transmitter with Forwarded Clock to Enable PAM-16 / 256-QAM and Channel Response Detection in 28 nm CMOS
(2016)
Du, Yuan
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Cho, Wei-Han
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Li, Yilei
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Wong, Chien-Heng
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Du, Jieqiong
A cognitive tri-band transmitter with forwarded clock using multi-band signaling and high-level digital signal modulations is presented for serial link application. The transmitter features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level, and accordingly adapts modulation scheme, data bandwidth and carrier frequency. The modulation scheme ranges from NRZ/QPSK to PAM-16/256-QAM. The highly re-configurable transmitter is capable of dealing with low-cost serial link cables/connectors or multi-drop buses with deep and narrow notches in frequency domain (e.g. 40dB loss at notches). The adaptive multi-band scheme mitigates equalization requirement and enhances the energy efficiency by avoiding frequency notches and utilizing the maximum available signal-to-noise ratio and channel bandwidth. The implemented transmitter consumes 14.7mW power and occupies 0.016mm(2) in 28nm CMOS. It achieves a maximum data rate of 16Gb/s per differential pair and the most energy-efficient FoM (defined in Fig. 8) of 20.4 mu W/Gb/s/dB considering channel condition.
A 256x128 energy-efficient TCAM with novel low power schemes
(2007)
Huang, Po-Tsang
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Chang, Shu-Wei
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Liu, Wen-Yen
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Hwang, Wei
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電子工程學系及電子研究所
Novel low power schemes for energy-efficient ternary content-addressable memory (TCAM) are presented in this paper. The butterfly match-line scheme is based on the pseudo-footless clock-data pre-charged architecture. It connects each pipelined stage in a butterfly style which significantly decreases both search time and power consumption. For applications like IP-address forwarding in a network router, a new don't-care based power gating and don't-care based hierarchical (DCBH) search-line scheme are proposed. The search-line is divided into global search-line (GSL) and local search-line (LSL) which is controlled by don't-care state in DCBH search-line scheme. Therefore, the power consumption on search line is reduced without any search time overhead. Besides, the power saving of the standby power is achieved by power gating technique. The proposed 256 x 128bit TCAM has been implemented with TSMC 0.13um CMOS technology. It shows 0.55ns of match evaluation time on search operation with 0.29 fJ/bit/search of energy efficiency.
A 38mW 40Gb/s 4-Lane Tri-Band PAM-4 / 16-QAM Transceiver in 28nm CMOS for High-Speed Memory Interface
(2016)
Cho, Wei-Han
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Li, Yilei
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Du, Yuan
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Wong, Chien-Heng
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Du, Jieqiong
A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop
(2008)
Chuang, Li-Pu
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Chang, Ming-Hung
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Huang, Po-Tsang
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Kan, Chih-Hao
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Hwang, Wei
A 333MHz-1GHz all-digital multiphase delay-locked loop with precise multi-phase output has been designed with TSMC 130nm CMOS technology model. A modified binary search algorithm is proposed to match up a linear approximate delay element (LADE). The LADE property of linearity and insensitive to PVT variations is good for digitally-controlled delay element. The lock-in time could be reduced down to 14 reference clock cycles, and enhance the operation range based on LADE[binary search algorithm co-operate effort. The timing error caused by process mismatch is further reduced by proposed rapid self-calibration (RSC) algorithm. A calibration unit is designed based on RSC algorithm, which reduces the maximum timing error to less than 9ps when DLL is operating at 500MHz. The entire calibration unit could be turned off after calibration procedure is complete to reduce power consumption. The total power dissipation of the all-digital self-calibrated multiphase delay-locked loop is 5.2mW at 1GHz with a 1.2V power supply.
A 64-CHANNEL WIRELESS NEURAL SENSING MICROSYSTEM WITH TSV-EMBEDDED MICRO-PROBE ARRAY FOR NEURAL SIGNAL ACQUISITION
(2017-01-01)
Huang, Yu-Chieh
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Huang, Po-Tsang
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Hu, Yu-Chen
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Wu, Shang-Lin
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You, Yan-Huei
To enhance the signal integrity of high-density neural-sensing signals, this work presents an implantable high spatial resolution mu-probe array with through-silicon via (TSV) 2.5D integration technology that realizes a miniaturized implantable device on flexible printed circuit (FPC) interposer. The proposed microsystem was composed of two 32-channel neural sensing chips and one radio frequency chip for neural signal processing. The mu-probe array can achieve better signal-to-noise ratio with neural-signal acquisition and processing circuit composed of a pseudo-resistor-based analog front-end amplifier. Moreover, a receiving antenna is also implemented on the backside of FPC for wireless data and power transmission. The feasibility of the proposed mu-probe array, Tx and Rx antenna, 32-channel neural sensing circuits in the 64-channel wireless microsystem have been successfully demonstrated for future integration and animal experiments.
A 65 nm 0.165 fJ/Bit/Search 256 x 144 TCAM Macro Design for IPv6 Lookup Tables
(2011-02-01)
Huang, Po-Tsang
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Hwang, Wei
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Ternary content addressable memory (TCAM) is extensively adopted in network systems. As routing tables become larger, energy consumption and leakage current become increasingly important issues in the design of TCAM in nano-scale technologies. This work presents a novel 65 nm energy-efficient TCAM macro design for IPv6 applications. The proposed TCAM employs the concept of architecture and circuit co-design. To achieve an energy-efficient TCAM architecture, a butterfly match-line scheme and a hierarchy search-line scheme are developed to reduce significantly both the search time and power consumption. The match-lines are also implemented using noise-tolerant XOR-based conditional keepers to reduce not only the search time but also the power consumption. To reduce the increasing leakage power in advanced technologies, the proposed TCAM design utilizes two power gating techniques, namely super cut-off power gating and multi-mode data-retention power gating. An energy-efficient 256 x 144 TCAM macro is implemented using UMC 65 nm CMOS technology, and the experimental results demonstrate a leakage power reduction of 19.3% and an energy metric of the TCAM macro of 0.165 fJ/bit/search.
A 65nm low power 2T1D embedded DRAM with leakage current reduction
(2007)
Chang, Mu-Tien
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Huang, Po-Tsang
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Hwang, Wei
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Gain cell memories feature high speed, low power, and high density, which are suitable for SoC designs. In this paper, low power techniques to reduce leakage currents for 2T1D gain cell memory array are presented. For each memory cell, p-type gated diode storage device is applied. In addition, footer power gating and foot driver are applied on each memory word. Simulation results show that the proposed 2T1D memory array structure has 97.7% and 80% standby power reduction over typical 2T1D and typical 3T1D memory array, respectively. All the simulation results are based on Predictive Technology Model (PTM) 65nm CMOS bulk technology.
A 7.5-mW 10-Gb/s 16-QAM Wireline Transceiver with Carrier Synchronization and Threshold Calibration for Mobile Inter-chip Communications in 16-nm FinFET
(2019-01-01)
Du, Jieqiong
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Wong, Chien-Heng
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Tu, Yo-Hao
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Cho, Wei-Han
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Li, Yilei
A compact energy-efficient 16-QAM wireline transceiver with carrier synchronization and threshold calibration is proposed to leverage high-density fine-pitch interconnects. Utilizing frequency-division multiplexing, the transceiver transfers four-bit data through one RF band to reduce inter-symbol interferences. A forwarded clock is also transmitted through the same interconnect with the data simultaneously to enable low-power PVT-insensitive symbol clock recovery. A carrier synchronization algorithm is proposed to overcome nontrivial current and phase mismatches by including DC offset calibration and dedicated I/Q phase adjustments. Along with this carrier synchronization, a threshold calibration process is used for the transceiver to tolerate channel and circuit variations. The transceiver implemented in 16-nm FinFET occupies only 0.006-mm(2) and achieves 10 Gb/s with 0.75-pJ/bit efficiency and <2.5-ns latency.
A double-sided, single-chip integration scheme using through-silicon-via for neural sensing applications
(2015-02-01)
Chang, Chih-Wei
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Chou, Lei-Chun
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Huang, Po-Tsang
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Wu, Shang-Lin
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Lee, Shih-Wei
We present a new double-sided, single-chip monolithic integration scheme to integrate the CMOS circuits and MEMS structures by using through-silicon-via (TSV). Neural sensing applications were chosen as the implementation example. The proposed heterogeneous device integrates standard 0.18 mu m CMOS technology, TSV and neural probe array into a compact single chip device. The neural probe array on the back-side of the chip is connected to the CMOS circuits on the front-side of the chip by using low-parasitic TSVs through the chip. Successful fabrication results and detailed characterization demonstrate the feasibility and performance of the neural probe array, TSV and readout circuitry. The fabricated device is 5x5 mm(2) in area, with 16 channels of 150 mu m-in-length neural probe array on the back-side, 200 mu m-deep TSV through the chip and CMOS circuits on the front-side. Each channel consists of a 5x6 probe array, 3x14 TSV array and a differential-difference amplifier (DDA) based analog front-end circuitry with 1.8 V supply, 21.88 mu W power consumption, 108 dB CMRR and 2.56 mu Vrms input referred noise. In-vivo long term implantation demonstrated the feasibility of presented integration scheme after 7 and 58 days of implantation. We expect the conceptual realization can be extended for higher density recording array by using the proposed method.
A low power pulsed edge-triggered latch for survivor memory unit of Viterbi decoder
(2006)
Su, Wei-Li
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Chiueh, Herming
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Huang, Po-Tsang
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Hwnag, Wei
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電信工程研究所
A low power pulsed edge-triggered latch based on the static edge-triggered latch (ETL) is presented for survivor memory (SMU) unit of Viterbi decoder for low power high speed wireless local area network (WLAN) applications. By reducing clock loading and transistor number, the proposed low swing static ETL has less clock loading, smaller cell area and power-delay product compared to traditional master-slave register. Moreover, a stage-reduced SMU is introduced later for saving both area and power consumption. The proposed low swing static ETL and stage-reduced SMU are designed and simulated in TSMC 0.13um standard CMOS process, and the operating clock frequency is at 1GHz.
A ROBUST ULTRA-LOW POWER ASYNCHRONOUS FIFO MEMORY WITH SELF-ADAPTIVE POWER CONTROL
(2008)
Chang, Mu-Tien
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Huang, Po-Tsang
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Hwang, Wei
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
First-in first-out (FIFO) memories are widely used in SoC for data buffering and flow control. In this paper, a robust ultra-low power asynchronous FIFO memory is proposed. With self-adaptive power control and complementary power gating techniques, leakage power of the FIFO memory array is minimized. Moreover, with the proposed dual-V(T) 7T SRAM cell, the FIFO memory has improved stability under ultra-low voltage supply. Simulation results show that the proposed scheme has 16% to 94% power reduction over conventional designs. The proposed scheme is implemented in UMC 90nm CMOS technology under 0.5V supply voltage, with 1.39uW power consumption at 5MHz reading frequency and 200kHz writing frequency.