Browsing by Author "Huang, Po-Yen"

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Cost-Effective and Variable-Channel FastICA Hardware Architecture and Implementation for EEG Signal Processing
(2016-01-01)
Van, Lan-Da
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Huang, Po-Yen
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Lu, Tsung-Che
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資訊工程學系
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Department of Computer Science
This paper proposes a cost-effective and variable-channel floating-point fast independent component analysis (FastICA) hardware architecture and implementation for EEG signal processing. The Gram-Schmidt orthonormalization based whitening process is utilized to eliminate the use of the dedicated hardware for eigenvalue decomposition (EVD) in the FastICA algorithm. The proposed two processing units, PU1 and PU2, in the presented FastICA hardware architecture can be reused for the centering operation of preprocessing and the updating step of the fixed-point algorithm of the FastICA algorithm, and PU1 is reused for Gram-Schmidt orthonormalization operation of preprocessing and fixed-point algorithm to reduce the hardware cost and support 2-to-16 channel FastICA. Apart from the FastICA processing, the proposed hardware architecture supports re-reference, synchronized average, and moving average functions. The cost-effective and variable-channel FastICA hardware architecture is implemented in 90 nm 1P9M complementary metal-oxide-semiconductor (CMOS) process. As a result, the FastICA hardware implementation consumes 19.4 mW at 100 MHz with a 1.0 V supply voltage. The core size of the chip is 1.43 mm(2). From the experimental results, the presented work achieves satisfactory performance for each function.
Demonstration of Using Digital FIR Filter and Matched Filter to Increase Data Rate in Visible Light Communication
(2013)
Liu, Yu-Feng
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Yeh, Chien-Hung
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Chow, Chi-Wai
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Huang, Po-Yen
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Liu, Yang
Using digital-filters in time domain are demonstrated to enhance the modulation-speed of 1 MHz bandwidth white LED communication. Digital FIR filter and matched filtering are used to reduce the inter-symbol-interference (ISI). Hence, 20-Mbps is achieved by using 4-ASK modulation.
Software Crash Analysis for Automatic Exploit Generation on Binary Programs
(2014-03-01)
Huang, Shih-Kun
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Huang, Min-Hsiang
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Huang, Po-Yen
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Lu, Han-Lin
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Lai, Chung-Wei
This paper presents a new method, capable of automatically generating attacks on binary programs from software crashes. We analyze software crashes with a symbolic failure model by performing concolic executions following the failure directed paths, using a whole system environment model and concrete address mapped symbolic memory in (SE)-E-2 We propose a new selective symbolic input method and lazy evaluation on pseudo symbolic variables to handle symbolic pointers and speed up the process. This is an end-to-end approach able to create exploits from crash inputs or existing exploits for various applications, including most of the existing benchmark programs, and several large scale applications, such as a word processor (Microsoft office word), a media player (mpalyer), an archiver (unrar), or a pdf reader (foxit). We can deal with vulnerability types including stack and heap overflows, format string, and the use of uninitialized variables. Notably, these applications have become software fuzz testing targets, but still require a manual process with security knowledge to produce mitigation-hardened exploits. Using this method to generate exploits is an automated process for software failures without source code. The proposed method is simpler, more general, faster, and can be scaled to larger programs than existing systems. We produce the exploits within one minute for most of the benchmark programs, including mplayer. We also transform existing exploits of Microsoft office word into new exploits within four minutes. The best speedup is 7,211 times faster than the initial attempt. For heap overflow vulnerability, we can automatically exploit the unlink() macro of glibc, which formerly requires sophisticated hacking efforts.