Browsing by Author "Huang, Rei-Fu"

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Alternate Hammering Test for Application-Specific DRAMs and an Industrial Case Study
(2012)
Huang, Rei-Fu
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Yang, Hao-Yu
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Chao, Mango C. -T.
;
Lin, Shih-Chin
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電子工程學系及電子研究所
This paper presents a novel memory test algorithm, named alternate hammering test, to detect the pairwise word-line hammering faults for application-specific DRAMs. Unlike previous hammering tests, which require excessively long test time, the alternate hammering test is designed scalable to industrial DRAM arrays by considering the array layout for potential fault sites and the highest DRAM-access frequency in real system applications. The effectiveness and efficiency of the proposed alternate hammering test are validated through the test application to an eDRAM macro embedded in a storage-application SoC.
Fault Models and Test Methods for Subthreshold SRAMs
(2010)
Lin, Chen-Wei
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Chen, Hung-Hsin
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Yang, Hao-Yu
;
Chao, Mango C-T
;
Huang, Rei-Fu
Due to the increasing demand of an extra-low-power system, a great amount of research effort has been spent in the past to develop an effective and economic subthreshold-SRAM design. However, the test methods regarding those newly developed subthreshold-SRAM designs have not yet been fully discussed. In this paper, we first categorize the subthreshold-SRAM designs into three types, study the faulty behavior of different open defects for each type of designs, and then identify the faults which may or may not be covered by a traditional SRAM test method. For those hard-to-detect faults, we will further discuss the corresponding test method according to different each type of subthreshold-SRAM designs. At last, a discussion about the temperature at test will also be provided.
Fault Models and Test Methods for Subthreshold SRAMs
(2013-03-01)
Lin, Chen-Wei
;
Chen, Hung-Hsin
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Yang, Hao-Yu
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Huang, Chin-Yuan
;
Chao, Mango C. -T.
Due to the increasing demand of an extra-low-power system, a great amount of research effort has been spent in the past to develop an effective and economic subthreshold SRAM design. However, the test methods regarding those newly developed subthreshold SRAM designs have not yet been fully discussed. In this paper, we first categorize the subthreshold SRAM designs into three types, study the faulty behavior of open defects and address decoders faults on each type of designs, and then identify the faults which may not be covered by a traditional SRAM test method. We will also discuss the impact of open defects and threshold-voltage mismatch on sense amplifiers under subthreshold operations. A discussion about the temperature at test is also provided.
Fault Models for Embedded-DRAM Macros
(2009)
Chao, Mango C. -T.
;
Yang, Hao-Yu
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Huang, Rei-Fu
;
Lin, Shih-Chin
;
Chin, Ching-Yu
In this paper, we compare embedded-DRAM (eDRAM) testing to both SRAM testing and commodity-DRAM testing, since an eDRAM macro uses DRAM cells with an SRAM interface. We first start from an standard SRAM test algorithm and discuss the faults which are not covered in the SRAM testing but should be considered in the DRAM testing. Then we study the behavior of those faults and the tests which can detect them. Also, we discuss how likely each modeled fault may occur on eDRAMs and commodity DRAMs, respectively.
Testing Methodology of Embedded DRAMs
(2012-09-01)
Yang, Hao-Yu
;
Chang, Chi-Min
;
Chao, Mango C. -T.
;
Huang, Rei-Fu
;
Lin, Shih-Chin
"The embedded-DRAM(eDRAM) testing mixes up the techniques used for DRAM testing and SRAM testing since an eDRAM core combines DRAM cells with an SRAM interface (the so-called 1T-SRAM architecture). In this paper, we first present our test algorithm for eDRAM testing. A theoretical analysis to the leakage mechanisms of a switch transistor is also provided, based on that we can test the eDRAM at a higher temperature to reduce the total test time and maintain the same retention-fault coverage. Finally, we propose a mathematical model to estimate the defect level caused by wear-out defects under the use of error-correction-code circuitry, which is a special function used in eDRAMs compared to commodity DRAMs. The experimental results are collected based on 1-lot wafers with an 16 Mb eDRAM core."
Testing Methodology of Embedded DRAMs
(2008)
Chang, Chi-Min
;
Chao, Mango C. -T.
;
Huang, Rei-Fu
;
Chen, Ding-Yuan
;
電子工程學系及電子研究所
The embedded-DRAM testing mixes up the techniques used for DRAM testing and SRAM testing since an embedded-DRAM core combines DRAM cells with an SRAM interface (the so-called IT-SRAM architecture). In this paper we first present our test algorithm for embedded-DRAM testing. A theoretical analysis to the leakage mechanisms of a switch transistor is also provided, based on that we can test the embedded-DRAM at a higher temperature to reduce the total test time and maintain the same retention-fault coverage. The experimental results art? collected based on I-lot wafers with an 16Mb embedded DRAM core.
Testing Methods for a Write-Assist Disturbance-Free Dual-Port SRAM
(2014)
Yang, Hao-Yu
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Lin, Chen-Wei
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Huang, Chao-Ying
;
Lu, Ching-Ho
;
Lai, Chen-An
The recent research works of dual-port SRAM have focused on developing new write-assist techniques to suppress the potential inter-port write disturbance under low operating voltage and high process variation. However, the testing related issues induced by those newly proposed write-assist techniques have not been discussed yet in the previous literatures. In this paper, we first implemented a new write-assist dual-port SRAM proposed in [10] by using a 28nm LP process and then discussed the faulty behavior of injecting different resistive-open defects into both the SRAM cell and write-assist circuit. Next, we developed new test methods to detect the hard-to-detect resistive-open defects and proposed a corresponding March-like algorithm that covers a widely used March C-as well as the proposed test methods. Last, the required DfT for the proposed test methods was also discussed.
Testing Methods for Quaternary Content Addressable Memory Using Charge-Sharing Sensing Scheme
(2015)
Yang, Hao-Yu
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Huang, Rei-Fu
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Su, Chin-Lung
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Lin, Kuan-Hong
;
Shu, Hang-Kaung
Due to its capability of parallel search, content addressable memory (CAM) has been widely used on the applications requiring high-speed data search. In recent years, the architectures and design techniques for CAM have been consistently evolving. However, the incoming testing issues for those newly evolved CAM designs are not fully discussed. In this paper, we investigate the testing issues for a new 28nm quaternary CAM, which provides the additional fourth state compared to a conventional ternary CAM and utilizes a charge-sharing sensing scheme for reducing its search power consumption. We first identify the new fault models for this quaternary CAM that are not covered in the conventional CAM testing based on the simulation result, and derive the corresponding test algorithm for those new fault models. The effectiveness of the proposed test algorithm is then validated by the testing result of 7200 28nm sample chips covering different process corners with the help of a newly designed command-based memory BIST.