Browsing by Author "Huang, Ryan H. -M."

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A Determinate Radiation Hardened Technique for Safety-Critical CMOS Designs
(2015-04-01)
Huang, Ryan H. -M.
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Hsu, Dennis K. -H.
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Wen, Charles H. -P.
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電機資訊學士班
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Undergraduate Honors Program of Electrical Engineering and Computer Science
Soft errors have been a critical concern for reliability of advanced CMOS designs due to technology scaling. Moreover, along with the rapid growth of medical, automotive, and aerospace electronics, extremely high demand on reliability becomes the paramount concern, superior to cost and performance, on these safety-critical designs. Triple modular redundancy (TMR) is widely used to mask virtually all soft errors but typically incurs high power and area overheads. Therefore, in this paper, a determinate radiation hardened technique for safety-critical CMOS designs is proposed and consists of three hybrid strategies combining gate sizing, supply voltage (V (D D) ) scaling and threshold voltage (V (t h) ) scaling to prevent soft errors from occurring. A STA-like method that computes the required pulse width of a transient fault along the propagation path is also developed in this framework. Simulation results show that the proposed technique can effectively eliminate all soft errors on ISCAS\'85 circuits and a controller area network bus electrical control unit (CAN-bus ECU) design for automotive electronics when the deposited charges range from 35 fC to 132 fC. Furthermore, the strategy using all three techniques, simultaneously improves power and area overheads by 3.3X and 2X, respectively, compared with TMR.
Aging-aware Statistical Soft-Error-Rate Analysis for Nano-Scaled CMOS Designs
(2013-01-01)
Lin, Cosette Y. H.
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Huang, Ryan H. -M.
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Wen, Charles H. -P.
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Chang, Austin C. -C.
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電機工程學系
Aging and soft errors have become the two most critical reliability issues for nano-scaled CMOS designs. In this paper, the aging effect due to negative bias temperature instability (NBTI) is first analyzed on cells using a 45nm CMOS technology for soft errors. Second, an accurate statistical soft-error-rate (SSER) framework is built and incorporates the aging-aware cell models. As a result, two findings are discovered: (1) PMOS-induced transient faults, comparing to NMOS-induced ones, have more variation in pulse widths since PMOS is more susceptible to NBTI; (2) NBTI together with process variation, induces more soft errors (similar to 19%) and thus needs to be considered, simultaneously, during circuit analysis. Experimental result shows that our SSER framework considering both process variation and aging is efficient (with multiple-order speedups) and achieves high accuracy (with <3% errors) when compared with Monte-Carlo SPICE simulation.
Aging-aware Statistical Soft-Error-Rate Analysis for Nano-Scaled CMOS Designs
(2013)
Lin, Cosette Y. H.
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Huang, Ryan H. -M.
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Wen, Charles H. -P.
;
Chang, Austin C. -C.
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電機資訊學士班
Aging and soft errors have become the two most critical reliability issues for nano-scaled CMOS designs. In this paper, the aging effect due to negative bias temperature instability (NBTI) is first analyzed on cells using a 45nm CMOS technology for soft errors. Second, an accurate statistical soft-error-rate (SSER) framework is built and incorporates the aging-aware cell models. As a result, two findings are discovered: (1) PMOS-induced transient faults, comparing to NMOS-induced ones, have more variation in pulse widths since PMOS is more susceptible to NBTI; (2) NBTI together with process variation, induces more soft errors (similar to 19%) and thus needs to be considered, simultaneously, during circuit analysis. Experimental result shows that our SSER framework considering both process variation and aging is efficient (with multiple-order speedups) and achieves high accuracy (with <3% errors) when compared with Monte-Carlo SPICE simulation.
CASSER: A Closed-Form Analysis Framework for Statistical Soft Error Rate
(2013-10-01)
Chang, Austin C. -C.
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Huang, Ryan H. -M.
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Wen, Charles H. -P.
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電機資訊學士班
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Undergraduate Honors Program of Electrical Engineering and Computer Science
CMOS designs in the deep submicrometer era require statistical methods to accurately estimate the circuit soft error rate (SER). However, process variation increases the complexity of statistical characteristics related to transient faults, leading to considerable uncertainty in the behavior of soft errors. Regardless of the methods used, current statistical SER (SSER) frameworks invariably involve a tradeoff between accuracy and efficiency. This paper presents accurate cell models in first-order closed form to overcome this problem, thereby enabling the analysis of SSERs in a block-based fashion similar to statistical static timing analysis. These cell models are derived as a closed form in the proposed framework named CASSER, and remain precise under the assumption of a normal distribution for the process parameters. Experimental results demonstrate the efficiency (> 2-order times faster than the latest framework) and accuracy (< 3% error) of CASSER in estimating circuit SERs, when compared with the Monte Carlo SPICE simulation.
Suppressing Test Inflation in Shared-Memory Parallel Automatic Test Pattern Generation
(2014-01-01)
Ku, Jerry C. Y.
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Huang, Ryan H. -M.
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Lin, Louis Y. -Z.
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Wen, Charles H. -P.
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資訊工程學系
Multi-core machines enable the possibility of parallel computing in Automatic Test Pattern Generation (ATPG). With sufficient computing power, previously proposed parallel ATPG has reached near linear speedup. However, test inflation in parallel ATPG yet arises as a critical problem and limits its practicality. Therefore, we developed a parallel ATPG system that incorporates (1) concurrent interruption (CI), (2) ripple compaction (RC) and (3) fan-in-cone based fault ordering (FIC) to deal with such problem. Concurrent interruption aborts test generation on simultaneously detected faults by fault simulation. Ripple compaction combines tests for different faults while fan-in-cone based fault ordering strategically arranges the fault list to reduce the number of test generations and thus speeds up the ATPG process. According to our experiments, the proposed parallel ATPG system effectively reduces 11% pattern count and achieves similar to 0% test inflation while maintaining an average of 6.5X speedup with no attenuation in fault coverage on experimental circuits.
TA-FTA: Transition-Aware Functional Timing Analysis with A Four-Valued Encoding
(2015)
Chang, Jasper C. C.
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Huang, Ryan H. -M.
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Lin, Louis Y. -Z.
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Wen, Charles H. -P.
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資訊工程學系
Timing analysis becomes profound for modern VLSI designs. Functional timing analysis (FTA) has emerged to eliminate false paths and provide better timing closure than traditional static timing analysis (STA). However, signal transitions effect, such as multiple input switching (MIS), which changes the pin-to-pin delay of a gate as well as the overall circuit delay, has not yet been considered in FTA. Therefore, a Transition-Aware FTA (TA-FTA) engine using a novel four-valued encoding for calculating true delay under the signal-transition effect is developed in this work. However, timing analysis becomes sophisticated once the signal-transition effect is concerned. Therefore, two techniques, cone separation and filtering (CSF) and quadratic dynamic search (QDS), are also proposed to speed up TA-FTA by more than two orders in time. Experimental results shows that after considering the MIS effect, in the benchmark circuits, the delay reported by our TA-FTA increases by 23% on average and by 38% for the worst case.
TASSER: A Temperature-Aware Statistical Soft-Error-Rate Analysis Framework for Combinational Circuits
(2014-01-01)
Hsueh, Sung S. -Y.
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Huang, Ryan H. -M.
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Wen, Charles H. -P.
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電機資訊學士班
;
Undergraduate Honors Program of Electrical Engineering and Computer Science
Soft error has become one of the most critical reliability issues for nano-scaled CMOS designs. Many previous works discovered that the pulse width due to a particle strike on the device increases with temperature, but its system-level effect has not yet been investigated with statistical soft-error-rate (SER). Therefore, in this paper, a combinational circuit (c17 from ISCAS\'85) using a 45nm CMOS technology is f rst observed under different temperatures for SER. As a result, a SER increase (2.16X more) is found on c17 as the ambient temperature elevates from 25 degrees C to 125 degrees C. Second, along with growing design complexity, the operational temperatures of gates are distributed in a wide range and much higher than the ambient temperature in reality. Therefore, we are motivated to build a temperature-aware SSER analysis framework that integrates statistical cell modeling to consider the ambient temperature (T-a) and the temperature variation (T-v), simultaneously. Experimental result shows that our SSER analysis framework is highly effcient (with multiple-order speed-ups) and accurate (with only <4% errors), when compared with Monte-Carlo SPICE simulation.
TASSER: A Temperature-Aware Statistical Soft-Error-Rate Analysis Framework for Combinational Circuits
(2015)
Hsueh, Sung S. -Y.
;
Huang, Ryan H. -M.
;
Wen, Charles H. -P.
;
電機學院
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College of Electrical and Computer Engineering
Soft error has become one of the most critical reliability issues for nano-scaled CMOS designs. Many previous works discovered that the pulse width due to a particle strike on the device increases with temperature, but its system-level effect has not yet been investigated with statistical soft-error-rate (SER). Therefore, in this paper, a combinational circuit (c17 from ISCAS\'85) using a 45nm CMOS technology is f rst observed under different temperatures for SER. As a result, a SER increase (2.16X more) is found on c17 as the ambient temperature elevates from 25 degrees C to 125 degrees C. Second, along with growing design complexity, the operational temperatures of gates are distributed in a wide range and much higher than the ambient temperature in reality. Therefore, we are motivated to build a temperature-aware SSER analysis framework that integrates statistical cell modeling to consider the ambient temperature (T-a) and the temperature variation (T-v), simultaneously. Experimental result shows that our SSER analysis framework is highly effcient (with multiple-order speed-ups) and accurate (with only <4% errors), when compared with Monte-Carlo SPICE simulation.