Browsing by Author "Huang, SR"

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An automated IP synthesizer for limited-resource DWT processor
(2002)
Wei, TH
;
Huang, SR
;
Dung, LR
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper presents a systematic design methodology for 1-D/2-D DWT processor based on a novel limited-resource scheduling algorithm. Given a set of architecture constraints and DWT parameters, the scheduling algorithm can generate four scheduling matrices that drive the data path to perform the DWT computation. Based on the limited-resource scheduling algorithm an automated DWT processor synthesizer has been developed and generates constrained DWT processors in the form of silicon intelligent property (SIP). The DWT SIP can be embedded into a SOC or mapped to program codes for commercial off-the-shelf (COTS) DSP processors with programmable devices. As a result, it has been successfully proven that a variety of DWT SIPs can be efficiently realized by tuning the parameters and applied for signal processing applications.
VLSI implememtation for MAC-level DWT architecture
(2002)
Huang, SR
;
Dung, LR
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper presents a VLSI design methodology for the MAC-level DWT processor based on a novel limited-resource scheduling (LRS) algorithm. The r-split Fully-specified Signal Flow Graph (FSFG) of limited-resource FIR filter has been developed for the scheduling of the MAC-level DWT signal processing. Given a set of architecture constraints and DWT parameters, the LRS algorithm can generate four scheduling matrices that drive the data path to perform the DWT computation, and the performance has also been investigated. Because the registers of FIR filtering are reused for the inter-octave storage, the MAC-level DWT architecture may require less extra inter-octave memory than the traditional architecture.