Browsing by Author "Huang, Shao-Chang"

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Avalanche Ruggedness Capability and Improvement of 5-V n-Channel Large-Array MOSFET in BCD Process
(2019-07-01)
Nidhi, Karuna
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Ker, Ming-Dou
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Lee, Jian-Hsing
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Huang, Shao-Chang
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交大名義發表
Energy handling capability of large-array devices (LADs) is one of the most dominating concerns for the designers that affect the device design and its reliability. In this paper, the improvement of the avalanche ruggedness capability by using an optional implantation layer has been investigated the first time for the application of 5-V n-channel large-array MOSFET in a bipolar-CMOS-DMOS (BCD) process. Experimental results with extensive measurements verified that the maximum avalanche current (I-AV) achieved from themodified device is enhanced by more than twice. Moreover, the energy in avalanche single pulse (EAS) capability is improved by more than five times. A significant improvement is noticed in the avalanche safe-operating-area (A-SOA) as compared to the original device, and the failure analysis is discussed in detail. In addition, the impact of an optional implantation layer on the total gate charge (Qg) is also compared for a LAD with a total width of 12 000 mu m.
Embedded I/O PAD Circuit Design for OTP Memory Power-Switch Functionality
(2012-04-01)
Huang, Shao-Chang
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Chen, Ke-Horng
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Lin, Wei-Yao
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Lee, Zon-Lon
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Chang, Kun-Wei
An additional high-voltage pad is generally applied for one-time-programming (OTP) memory product applications. This may increase the complexity of input/output (I/O) pad arrangement and the area penalty. In this paper, a novel approach of I/O circuit embedded with the power-switch function is proposed for multifunction integrations in one I/O pad. The capabilities of high-voltage programming, I/O signal handling, electrostatic discharge protection and latch-up prevention for this novel circuit are well examined from silicon verifications.
Energy Transformation Between the Inductor and the Power Transistor for the Unclamped Inductive Switching (UIS) Test
(2020-06-01)
Nidhi, Karuna
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Lee, Jian-Hsing
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Huang, Shao-Chang
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Ker, Ming-Dou
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交大名義發表
The fundamental model of energy transformation between the inductor and the power transistor for the unclamped inductive switching (UIS) test is inspected. Based on the experimental results, the energy stored in the inductor at the period of the channel turn-on can be dissipated by the power transistor after the channel is turned off. In this work, a new theoretical model to well describe the electrical and thermal behaviors of the power transistor during the unclamped inductive switching (UIS) test has been identified and analyzed with the experimental silicon results under different inductor values in 0.15 mu m BCD process. The total UIS energy reduced due to series resistance of the inductor and the power transistor has been theoretically explained and well matches with the experimental measured results on silicon.
ESD Avoiding Circuits for Solving OTP Memory Falsely Programmed Issues
(2010)
Huang, Shao-Chang
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Chen, Ke-Horng
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Chen, Hsin-Ming
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Ho, Ming-Chou
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Shen, Rick Shih-Jye
One-time program (OTP) memories are programmed for memory design without electrostatic discharge (ESD) stresses. However, in reality, ESD events are not selective and thus ESD currents can falsely program OTP memory cells. Many integrated circuit (IC) designers focus only on improving OTP memory control architectures to avoid memory being falsely programmed without mentioning the ESD-introduced memory errors. This article investigates a new ESD architecture and novel ESD avoiding circuits, aiming to solve ESD-introduced memory falsely programmed issues. It should be noted that this article focuses on ESD circuit designs to protect OTP memory instead of OTP control architectures. With such new ESD schemes, our prototype circuits have demonstrated that memory cells can indeed be programmed at IC program mode without ESD stresses.
Fast Transient (FT) Technique With Adaptive Phase Margin (APM) for Current Mode DC-DC Buck Converters
(2012-10-01)
Lee, Yu-Huei
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Huang, Shao-Chang
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Wang, Shih-Wei
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Chen, Ke-Horng
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電控工程研究所
This paper proposes a fast transient (FT) control with the adaptive phase margin (APM) to achieve good transient response in current-mode DC-DC buck converters at different load conditions. The overshoot/undershoot voltage and the transient recovery time are effectively reduced. The APM control can always maintain the system phase margin at an adequate value under different load conditions. That is, the compensation pole-zero pair is adapted to load current to extend the system bandwidth and get an adequate phase margin. Experimental results show the overshoot/undershoot voltage is smaller than 60 mV (3%) and transient period is smaller than 12 mu s as load current suddenly changes from 100 to 500 mA, or vice versa. Compared with conventional designs without any fast transient technique, the undershoot voltage and recovery time are enhanced by 45% and 85%, respectively.
Multi-color LC/BL algorithm in field-sequential-color LCD for color-breakup suppression
(2011-02-01)
Huang, Shao-Chang
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Chu, Chun-Li
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Chiu, Ta-Liang
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Chen, Ke-Horng
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電控工程研究所
The proposed liquid-crystal and backlight (LC/BL) algorithm presents the dynamic field-sequential-color (D-FSC) algorithm to reduce the color-breakup (CBU) effect without greatly increasing the subframe rate. The D-FSC algorithm can intelligently select one adequate color sequence from multiple color sequences according to the image data. In other words, the scope of CBU suppression of the proposed LC/BL algorithm is more extensive than other conventional FSCs. Simulation results show that the CBU suppression can be improved substantially by the proposed evaluation equation.
Package and Chip Accelerated Aging Methods for Power MOSFET Reliability Evaluation
(2019-01-01)
Lin, Tingyou
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Su, Chauchin
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Hung, Chung-Chih
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Nidhi, Karuna
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Tu, Chily
This paper investigates power MOSFET stress strategies for both package and chip aging evaluation. Two stress test methods are developed to speed up packaging and chip aging process respectively. As a result, the characteristics shifts of package and chip aging can be plotted independently. Thus, the measurement accuracy and measurement time can be improved. A test chip is designed and fabricated in a 0.15tm BCD process. The measured results demonstrate a 10kjtm power MOSFET has R-on increased by 72% after 6.3hr stress for the package aging. For the chip aging, the MOSFET has R-on increased by 12% after 600 times stress pulses. The measurement verifies that the accelerated aging in the package and the chip can be controlled separately.
Power-Tracking Embedded Buck-Boost Converter With Fast Dynamic Voltage Scaling for the SoC System
(2012-03-01)
Lee, Yu-Huei
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Huang, Shao-Chang
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Wang, Shih-Wei
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Wu, Wei-Chan
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Huang, Ping-Ching
A power-tracking embedded buck-boost converter with a fast dynamic voltage scaling (F-DVS) function is proposed to power the system-on-a-chip (SoC) system. To meet the power request of the SoC for different operation functions, fast up/down-tracking is implemented to achieve the F-DVS function. Recycling energy is also derived to minimize power dissipation during the down-tracking period. In addition, the peak current control and valley current control methods are utilized in the buck and boost operations, respectively, to minimize the effect of switching noise in high switching operation for compact solution. Moreover, the self-tuning pulse skipping mechanism extends the effective duty cycle to achieve voltage regulation and improves efficiency when the input voltage is close to that of the output. Through F-DVS, the tracking speed from 3 to 2 V and vice versa are 15 and 20 mu s, respectively, with a high switching frequency of 5 MHz.
Semiself-Protection Scheme for Gigahertz High-Frequency Output ESD Protection
(2011-07-01)
Lee, Jian-Hsing
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Huang, Shao-Chang
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Su, Hung-Der
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Chen, Ke-Horng
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電控工程研究所
In this paper, a semiself-protection scheme is proposed and developed for gigahertz output electrostatic-discharge (ESD) protection. The output transistor acts as a trigger device to trigger the ESD protection device, and then, it is turned off when the ESD protection device turns on. Thus, the capacitance of a gigahertz high-frequency output pad can be minimized because this scheme is without any additional trigger device or any passive component.
Substrate Pick-Up Impacting on ESD Performances of Cascode NMOS Transistors
(2011-02-01)
Huang, Shao-Chang
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Chen, Ke-Horng
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電機工程學系
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電控工程研究所
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Department of Electrical and Computer Engineering
The cascode NMOS architecture has been tested by the Human Body Model (HBM), Machine Model (MM) and Transmission Line Pulse Generator (TLP) in this paper. For the TLP, detailed silicon data have been analyzed well in many parameters, such as the first triggering-on voltage (Vt1), the first triggering-on current (It1), the holding voltage (Vh), and the TLP I-V curve. Besides the above three kinds of Electrostatic Discharge (ESD) events, the device gate oxide breakdown voltage is also taken into consideration and the correlations between HBM, MM and TLP are also observed. In order to explain the bipolar transistor turning-on mechanisms, two kinds of models have been proposed in this paper. In typical cases, substrate resistance decreases as the technology advances. On the one hand, for processes older than the 0.35 mu m process, such as 0.5 mu m and 1 mu m, ESD designers can use pick-up insertions to trigger integrated circuits (IC) turn on uniformly. The NPN Side Model can dominate ESD performances in such old processes. On the other hand, in 0.18 mu m and newer processes, such as 0.15 mu m, 0.13 mu m, 90 nm, etc., ESD designers must use non-pick-up insertion structures. The NPN Central Model can dominate ESD performances in such processes. After combining both models together, the bipolar turning-on mechanisms can be explained as "ESD currents occur from side regions to central regions." Besides ESD parasitic bipolar transistor turning-on concerns, another reason that ESD designers should use non-pick-up insertions in deep sub-micron processes is the decreasing of the gate oxide breakdown voltage. As IC size scales down, the gate oxide thickness lessens. The thinner gate oxide thickness will encounter a smaller gate oxide breakdown voltage. In order to avoid gate oxide damage under ESD stresses, ESD designers should endeavor to decrease ESD device turn-on resistances. ESD protecting devices with low tum-on resistances can endure larger currents for the same TLP voltage. In this paper, silicon data show that the non-pick-up insertion cascode NMOS transistor's turning on resistance is smaller than the pick-up insertion cascode NMOS transistor's turning on resistance. Although this paper discovers NPN turning-on mechanisms based on the cascode NMOS structure, ESD designers can adopt the same theories for other kinds of ESD protecting structures, such as one single poly Gate-Grounded NMOS transistor (GGNMOST). ESD designers can use pick-up insertion architecture for NMOS transistors in the low-end processes, but utilize the non-pick-up insertion architecture for GGNMOST in the high-end processes. Then they can obtain the optimized ESD performances.
Two-stage trigger silicon-controller rectifier (SCR) for radio-frequency (RF) input and output protections in nanometer technologies
(2012-08-01)
Lee, Jian-Hsing
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Wu, Yi-Hsun
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Huang, Shao-Chang
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Lee, Yu-Huei
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Chen, Ke-Horng
In this paper, a two-stage trigger (TST) scheme is proposed to implement a low-capacitance and zero-ohm input resistance electrostatic-discharge (ESD) protection device for nanometer technology applications. Besides the main trigger device diode string, the output transistor can also be used as the trigger device. The dimension of the main trigger device can be reduced for minimizing its capacitance with the additional trigger device. Moreover, the output transistor can be as the driving device without any series resistor. This is because the diode string can help to prevent integrated circuits (ICs) from ESD damage before the primary ESD protection device turns on. (c) 2012 Elsevier Ltd. All rights reserved.