Browsing by Author "Huang, Shen-Jui"

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A 802.15.3c/802.11ad Compliant 24 Gb/s FFT Processor for 60 GHz Communication Systems
(2015)
Davila, Henry Lopez
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Liu, Chun-Yi
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Liu, Wei-Chang
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Huang, Shen-Jui
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Jou, Shyh-Jye
This paper, we present a 24 Gb/s 512-point 8X-parallel FFT processor for 60 GHz communication systems. The proposed design is a pipelined Multipath Delay Feedback (MDF) radix-2(3) architecture, which exploits the parallelism of the multipath scheme together with pipeline technique to achieve a high throughput rate. Besides, the proposed FFT processor is implemented with an area efficient optimized multiplier architecture that avoid the need to store the twiddle factor in memory and a dynamic scaling technique to enhance the SQNR, allowing the FFT to operate with 16-QAM and 64-QAM for single carrier (SC) and orthogonal frequency-division multiplexing(OFDM) schemes. This FFT processor has been implemented in a SC/OFDM dual-mode baseband receiver satisfying the requirements of the 802.15.3c/802.11ad standard with a 40nm CMOS process. The post-layout implementation results show that the proposed FFT processor is able to achieve up to 24 Gb/s throughput rate at 500MHz clock with a power consumption of 87mW and area of 0.64mm(2).
A High-Parallelism Memory-Based FFT Processor with High SQNR and Novel Addressing Scheme
(2016)
Huang, Shen-Jui
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Chen, Sau-Gee
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents an area-efficient memory-based FFT processor for long FFT lengths. To achieve high throughput, radix-4(2) FFT algorithm is adopted to reduce number of FFT stages. For low-complexity realization of the main butterfly processing element, a folded-by-2 scheme along with an optimized scheduling is designed. Variable FFT lengths (i.e., 1024 similar to 32768 points) can be supported through flexible switch configurations. Moreover, a conflict-free memory addressing scheme is devised to support 16-way parallel and normal-order data input/output without re-ordering buffers. An optimized block floating-point (BFP) scheme is employed for long-length FFT operations. The EDA synthesis results with TSMC-90nm process show that the area of proposed FFT processor is 2.98 mm(2), and the power consumption is 29 mW @160MHz clock frequency. The SQNR performance is over 70dB for all supported FFT lengths with 16-bit wordlength.
A High-Throughput Radix-16 FFT Processor With Parallel and Normal Input/Output Ordering for IEEE 802.15.3c Systems
(2012-08-01)
Huang, Shen-Jui
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Chen, Sau-Gee
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
"This paper presents a high-throughput FFT processor for IEEE 802.15.3c (WPANs) standard. To meet the throughput requirement of 2.59 Giga-samples/s, radix-16 FFT algorithm is adopted and reformulated to an efficient form so that the required number of butterfly stages is reduced. Specifically, the radix-16 butterfly processing element consists of two cascaded parallel/pipelined radix-4 butterfly units. It facilitates low-complexity realization of radix-16 butterfly operation and high operation speed due to its optimized pipelined structure. Besides, a new three-stage multiplier for twiddle factor multiplication is also proposed, which has lower area and power consumption than conventional complex multipliers. Moreover, a conflict-free multibank memory addressing scheme is devised to support up to 16-way parallel and normal-order data input/output. Without needing to reorder the input/output data, this scheme helps a high-throughput design result. Equipped with those new performance-boosting techniques, overall the proposed radix-16 FFT processor is area-efficient with high data processing rate and hardware utilization efficiency. The EDA synthesis results show that whole FFT processor area is mm, and the power consumption is 42 mW with 90 nm process. The SQNR performance is 57 dB with 12-bit wordlength implementation."
A Low-Complexity Mixed-Radix FFT Rotator Architecture
(2018-01-01)
Tsai, Wei-Lun
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Chen, Sau-Gee
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Huang, Shen-Jui
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
FFT-based OFDM and SC-FDMA transmission technologies have been widely adopted in most advanced telecommunication systems. For future 5G mobile communication systems, FFT again is expected to play very crucial roles. As such, design of FFT processors with unprecedentedly high performance has become a hard challenging problem that must be overcome. Among the components of an FFT processor, the rotator composed of ROMs and multipliers for twiddle factor multiplications take up the most area and power consumption. In order to reduce the cost, a reconfigurable multiplier-less and ROM-less rotator design approach is proposed in this paper. This approach supports both power-of-two and non-power-of-two FFT lengths. It effectively reduces the area by applying a series of decomposition and sharing schemes. An example of a rotator supporting 128-2048/1536-point FFT processor for the 4G LTE system is implemented with TSMC 90nm CMOS technology. Compared to the existing design, this work has 16.75% area reduction and 62.94% power reduction.
A MEMORY-EFFICIENT CONTINUOUS-FLOW FFT PROCESSOR FOR WIMAX APPLICATION
(2012)
Huang, Shen-Jui
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Chen, Sau-Gee
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交大名義發表
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National Chiao Tung University
This paper presents an area-efficient continuous-flow FFT/IFFT processor for Wimax application. Especially, the integration design of FFT processors with other functional blocks is considered according to Wiamx specification. A new memory scheduling scheme targeted for UL-PUSC transmission mode is proposed to reduce about 50% total memory space requirement compared with the conventional ping-pong based approach. In addition, a cascaded and pipelined PE structure is designed for high speed operation. The structure is configurable to support different FFT size efficiently, especially for those non-power-of-8 DFT operations. The EDA synthesis results show that the proposed FFT processor occupies only 1.62 mm(2) area based on TSMC 0.18-um process.
A New Memoryless and Low-latency FFT Rotator Architecture
(2014)
Huang, Shen-Jui
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Chen, Sau-Gee
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電機工程學系
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Department of Electrical and Computer Engineering
This paper presents new rotator architecture for FFT computation. The proposed architecture consists of cascaded multiplier-less cells, and each cell stage performs partial twiddle factor multiplications with low-complexity adders and multiplexers. Besides, for further area reduction, each cell is optimized with the technique of common subexpression sharing. Since those twiddle factors involved in computation are realized with multipliers generated on-the-fly by a scheme of coefficient selection, the proposed architecture doesn\'t require memory space to store any twiddle factors. Variable FFT lengths ranging from 64 similar to 32768 points can be supported by flexibly adding or removing some cell stages, depends on FFT length. Compared to CORDIC-based architectures, the proposed architecture has lower latency. The implementation results show that the proposed architecture is area-efficient and is suitable for either pipelined or memory based FFT architectures.
A SC/HSI Dual-Mode Baseband Receiver with Frequency-Domain Equalizer for IEEE 802.15.3c
(2013)
Liu, Wei-Chang
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Yeh, Fu-Chun
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Wei, Ting-Chen
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Huang, Ya-Shiue
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Liu, Tai-Yang
In this paper, an 8X-parallelism digital baseband receiver is proposed for IEEE 802.15.3c application. The baseband receiver consists of all-digital synchronization, radix-16 FFT and LS-LMS equalizer modules. It supports SC and HSI dual-mode in IEEE 802.15.3c with single hardware for area efficiency. The chip is implemented with 65 nm 1P9M process. The fabricated area is 12.96 mm(2) with 3463 K gate counts. The post-layout verification shows the throughput rate under QPSK modulation achieves 3.52 Gb/s and 5.28 Gb/s for SC mode (220 MHz) and HSI mode (330 MHz), respectively.
An IEEE 802.15.3c/802.11ad Compliant SC/OFDM Dual-Mode Baseband Receiver for 60 GHz Band
(2014-01-01)
Liu, Wei-Chang
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Yeh, Fu-Chun
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Wu, Chia-Yi
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Wei, Ting-Chen
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Huang, Ya-Shiue
In this paper, a dual-standard, dual-mode baseband receiver for 60 GHz wireless communication is presented. The receiver is designed to support SC and OFDM modes for both IEEE 802.15.3c and IEEE 802.11ad standards. The receiver is integrated with all-digital synchronization, radix-16 FFT, phase noise cancellation and low-complexity time-domain equalizer for line-of-sight channel application. The hardware utilization achieves 70% by leveraging hardware sharing between two modes and two standards for area efficiency. The receiver is implemented with 65 nm 1P9M process in 7.95 mm(2) core area. With feed-through architecture, the throughput rate supports up to 7.04 Gb/s and 15.84 Gb/s for SC mode (220 MHz) and OFDM mode (330 MHz), respectively.
Continuous-flow Parallel Bit-Reversal Circuit for MDF and MDC FFT Architectures
(2014-10-01)
Chen, Sau-Gee
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Huang, Shen-Jui
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Garrido, Mario
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Jou, Shyh-Jye
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電子工程學系及電子研究所
This paper presents a bit reversal circuit for continuous-flow parallel pipelined FFT processors. In addition to two flexible commutators, the circuit consists of two memory groups, where each group has P memory banks. For the consideration of achieving both low delay time and area complexity, a novel write/read scheduling mechanism is devised, so that FFT outputs can be stored in those memory banks in an optimized way. The proposed scheduling mechanism can write the current successively generated FFT output data samples to the locations without any delay right after they are successively released by the previous symbol. Therefore, total memory space of only N data samples is enough for continuous-flow FFT operations. Since read operation is not overlapped with write operation during the entire period, only single-port memory is required, which leads to great area reduction. The proposed bit-reversal circuit architecture can generate natural-order FFT output and support variable power-of-2 FFT lengths.
Feedforward FFT Hardware Architectures Based on Rotator Allocation
(2018-02-01)
Garrido, Mario
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Huang, Shen-Jui
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Chen, Sau-Gee
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電機工程學系
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Department of Electrical and Computer Engineering
In this paper, we present new feedforward FFT hardware architectures based on rotator allocation. The rotator allocation approach consists in distributing the rotations of the FFT in such a way that the number of edges in the FFT that need rotators and the complexity of the rotators are reduced. Radix-2 and radix-2(k) feedforward architectures based on rotator allocation are presented in this paper. Experimental results show that the proposed architectures reduce the hardware cost significantly with respect to previous FFT architectures.
Reconfigurable Radix-2(k)x3 Feedforward FFT Architectures
(2019-01-01)
Tsai, Wei-Lun
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Chen, Sau-Gee
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Huang, Shen-Jui
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Due to the increasing demand for high-throughput and low-cost mobile devices, design of high-parallel reconfigurable FFT processors has become more and more important. However, FFT lengths varied, designing a multi-length FFT processor with the requirement meet has become unprecedentedly challenging, especially as the FFT lengths includes non-power-of-two. In this paper, reconfigurable mixed-radix 2(k)x3-point feedforward FFT architectures are proposed. It can be realized as any power-of-two parallelism to achieve the sweet spot, with performs high enough to meet the requirement and still promise a reasonable cost. A proposed feedforward radix-3 FFT is applied in the architecture, empowering the FFT processor to achieve high parallelisms. An 8-parallel 1282048/1536-point FFT processor for the 4G LTE system is implemented with TSMC 90nm technology. Compared to the existing designs, this work offers a high-throughput and high area-efficiency solution for mixed-radix FFT operation.
The Serial Commutator FFT
(2016-10)
Garrido, Mario
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Huang, Shen-Jui
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Chen, Sau-Gee
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Gustafsson, Oscar
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電子工程學系及電子研究所
This brief presents a new type of fast Fourier transform (FFT) hardware architectures called serial commutator (SC) FFT. The SC FFT is characterized by the use of circuits for bit-dimension permutation of serial data. The proposed architectures are based on the observation that, in the radix-2 FFT algorithm, only half of the samples at each stage must be rotated. This fact, together with a proper data management, makes it possible to allocate rotations only every other clock cycle. This allows for simplifying the rotator, halving the complexity with respect to conventional serial FFT architectures. Likewise, the proposed approach halves the number of adders in the butterflies with respect to previous architectures. As a result, the proposed architectures use the minimum number of adders, rotators, and memory that are necessary for a pipelined FFT of serial data, with 100% utilization ratio.