Browsing by Author "Huang, Shin-Yi"

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A hybrid nanoparticle matrix for mass spectrometry
(2013)
Li, Po-Han
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Huang, Shin-Yi
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Chen, Yu-Chie
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Urban, Pawel L.
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應用化學系
We demonstrate hybrid inorganic-organic nanoparticles -based on silicon dioxide and 9-aminoacridine- which can enhance mass spectrometric analysis and imaging in the negative-ion mode. The nanoparticles bind to the surface of cells while still in the liquid phase, which is followed by a controlled release of the organic matrix molecules triggered by alkaline ammonia vapours delivered to the specimen in a closed chamber. First, the method was optimized and tested using standard compounds as analytes. Second, the spatial resolution was verified using a natural fibre (diameter similar to 20 mu m). Third, the method was used in the imaging of molecules present in the outer layer of large algal cells (Closterium acerosum). An important advantage of this method is that nanoparticles loaded with organic matrix can be applied to the biological cells as aqueous suspensions; hence, the release and spreading of metabolites can be limited during sample preparation for MALDI-MS. In addition, since this method does not involve spraying, exposure of experimenters to toxic aerosols is decreased.
An RDL-First Fan-Out Panel-Level Package for Heterogeneous Integration Applications
(2019-01-01)
Lin, Yu-Min
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Wu, Sheng-Tsai
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Wang, Chun-Min
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Lee, Chia-Hsin
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Huang, Shin-Yi
Technologies of Fan-outpanel-level packaging (FOPLP) are studies in this paper. First, the warpage control of a molded panel is a crucial problem for FOWLP technology development. In this paper, finite element analysis (FEA) is applied to study the influence of back end of the line (BEOL) process-induced warpage, as well as characterization for simulation, and investigation of each single process. In our process, a liquid release material is coated onto a 370 mm x 470 mm glass carrier. After baking, three layers of redistribution layer (RDL), passivation, and Cu leads are fabricated on the panel with coating, exposing, developing, lithography, and electroplating processes. Silicon test chips with a size of 16 mm x 10 mm and micro solder bumps with a pitch of 90 mu m are thinned down to 150 mu m. Test chips are then flip-chip bonded onto glass carrier with pre-bond and reflow proces. After panel molding, a laser debonding method, another key technology advancement, is utilized for panel debond. Debond performance, which is directly related to laser parameter and panel-level package (PLP) structure, is critical. After debonding, the molded panel is cleaned, followed by dicing and OSP coating processes, and then the electrical performance of the interconnection is evaluated. Reliability tests at the component level, such as pre-condition, thermal cycling test (TCT), and unbiased HAST (uHAST), are performed. The demonstration of RDL-first PLP technology without interposers proves its great potential in heterogeneous integration applications.
An RDL-First Fan-out Wafer-level Package for Heterogeneous Integration Applications
(2018-01-01)
Lin, Yu-Min
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Wu, Sheng-Tsai
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Shen, Wen-Wei
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Huang, Shin-Yi
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Kuo, Tzu-Ying
Fan-out wafer-level packaging (FOWLP), a new heterogeneous integration technology, is gradually becoming an attractive solution. Compared with conventional 2.5D/3D IC structures, fan-out WLP does not use a costly interposer element and can have a thin, high-density, and low-cost IC packaging. In this study, a novel fan-out WLP with RDL-first method is demonstrated. Finite element method was used to optimize the warpage control of a reconstituted wafer and to identify the material properties and fabrication for the FOWLP. Calculation results were applied in the design of the test vehicle. Reliability testing of each component level was performed with different techniques such as temperature cycling test (TCT), high temperature storage (HTS) and thermal humidity storage test (THST). The demonstration of RDL-first WLP technology without interposer proves that it has excellent potential for heterogeneous integration applications.
Effect of Joint Shape Controlled by Thermocompression Bonding on the Reliability Performance of 60 mu m-pitch Solder Micro Bump Interconnections
(2014-01-01)
Huang, Yu-Wei
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Zhan, Chau-Jie
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Juang, Jing-Ye
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Lin Yu-Min
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Huang, Shin-Yi
Three dimensional integration circuits technology has received much attention recently since the demands of functionality and performance in microelectronic packaging for electronic products are rapidly increasing. For high-performance 3D chip stacking, high density interconnections are essential. In the current types of interconnects, solder micro bumps have been widely used and thermocompression bonding process are well adopted to form the connection between bumps. However, the prefect joint contour is difficult to obtain and control by such kind of bonding process in solder micro bump joints. For fine-pitch solder micro bump interconnections, the effect of joint shape on the reliability performances of the solder micro bump joints is not concluded yet till now and needs to be clarified. In this study, the effect of joint shape controlled by thermocompression bonding on the reliability performance of solder micro bump interconnections with a pitch of 60 mu m was discussed. The chip-to-chip test vehicle having more than 4000 solder micro bump interconnections with a bump pitch of 60 mu m was used in this study. A solder micro bump structure of Cu/SnAg having a thickness of 7 mu m/10 mu m was fabricated in both the silicon chip and substrate. To evaluate the effect of joint shape, four types of joint shape were controlled and made. The first type had a conventional shape of micro joint. Compared to the first one joint structure, the second type of joint structure showed the compressed shape. The third type of joint structure was the pillar-like micro joint while the fourth type of joint structure presented a neck shape having the highest joint height among all the joint structures tested. We used the fluxless thermocompression bonding process to form these four types of micro joints. After bonding process, the chip stack was assembled by capillary-type underfill. Reliability tests of temperature cycling test (TCT), high temperature storage (HTS) and electromigration test (EM) were selected to assess the effect of joint shape on the reliability properties of those four types of solder micro bump interconnections. The reliability results presented that all the types of joint structures could pass TCT of 1000 cycles and HTS of 1000 hours but high variation of daisy chain resistance more than 15% would happen in the neck-shape micro joint after TCT. For the neck-shape micro joint, the high variation of daisy chain resistance after TCT resulted from the cracking propagated along the interface of Cu UBM/Cu6Sn5 IMC and across the tin solder. The cracking situation was more serious as compared to the other three tested micro joints. The results of HTS revealed that resistance variation mainly depended on the micro structural evolution within micro joints tested. Electromigration test was conducted under the testing condition of 0.56 A/150 degrees C. A daisy chain structure was adopted. For both the pillar-shape and neck-shape micro joints, Cu UBM consumption and formation of large void were the major microstructure evolutions within the micro interconnections during EM testing. The conpressed-shape showed the longer electromigration lifetime among all the types of micro joints tested.
Magnetic Nanoparticle-Based Platform for Characterization of Histidine-Rich Proteins and Peptides
(2013-03-19)
Huang, Shin-Yi
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Chen, Yu-Chie
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應用化學系
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Department of Applied Chemistry
In this study, we developed a platform that can be used to rapidly enrich polyhistidine(His)-tagged proteins/peptides from complex samples selectively using the Fe3O4@Al2O3 magnetic nanoparticles (MNPs) as the affinity probes. At pH 7, the dissociation constant between poly-His, i.e., His(6), and the Fe3O4@Al2O3 MNPs was similar to 10(-5) M and the trapping capacity was similar to 100 nmol/mg for His(6). Enrichment was achieved by vigorously mixing the sample solution (<2 mu L) and the MNPs (1-3 mu g) by pipetting directly onto a matrix-assisted laser desorption/ionization (MALDI) plate for 10 s. The time for the enrichment and the sample volume required for analysis are therefore greatly reduced. After enrichment, the MNP-target species conjugates were promptly isolated by positioning a magnet on the edge of the sample well to aggregate the conjugates into a small spot within similar to 5 so that the nontarget species could be easily removed. Additionally, the problem of finding "sweet spots" on the target species during the MALDI mass spectrometry (MS) analysis was greatly reduced by magnetically isolating the target species on the MALDI plate. The limit of detection for His(6) was, therefore, as low as similar to 400 amol. His(6) and AHHAHHAAD AHHAHHAAD spiked in a protein digest and in human plasma, respectively, were used as the samples to demonstrate the practicability of this approach in selective enrichment of His-rich peptides from complex samples. We also characterized His(6)-tagged proteins enriched on-plate by the Fe3O4@Al2O3 MNPs followed by on-plate tryptic digestion, selective enrichment, and MALDI-MS analysis. This approach can be used to determine quickly whether His(6)-tagged species are present in a sample. In addition, cell lysates containing recombinant Shiga-like toxins tagged with His(6) were used as the samples to further demonstrate that the feasibility of this approach in analyzing very complex samples. The entire analysis process, including the on-plate enrichment and enzymatic digestion followed by MALDI-MS analysis, can be completed within 10 min.
Optimization of laser release process for throughput enhancement of fan-out wafer-level packaging
(2018-01-01)
Lee, Chia-Hsin
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Su, Jay
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Liu, Xiao
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Wu, Qi
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Lin, Jim-Wein
Fan-out wafer-level-packaging (FOWLP) technology has been developed with various advantages, such as smaller form factor, lower cost, and simplified supply chain for heterogeneous integration. There have been several process schemes like chip-first or chip-last FOWLP integration discussed widely in conferences in recent years. One process in all of these process schemes has in common is the use of a temporary carrier for subsequent redistribution layer (RDL) formation, chip stacking and molding processes. Although the separation of a temporary carrier from the reconstituted wafer could be achieved without significant hurdles, there were few studies addressing optimization of carrier separation for throughput enhancement. Thus, this paper is designed to address the needs in optimizing carrier separation process based upon laser ablation technology. Two phases of experiments were designed to select the appropriate laser release layer and define optimal laser settings. The first experiment was used to evaluate correlation of the laser absorption, laser energy, and spot pitch versus completeness of laser ablation. The second experiment included RDL-first FOWLP integration. At first, 300-mm glass carriers (1000 mu m thick) with coefficient of thermal expansion of 8 ppm/degrees C were treated by selected laser release layers. After deposition of 0.05-mu m Ti/0.15 mu m Cu on the glass carrier, passivation of around 8 mu m was coated and patterned by lithography for electroplating Cu interconnections with a density of approximately 10% of the surface area. Subsequently, die bonding, build-up layers, or molding compound were applied on top to form a 200-mu m reconstituted wafer. The reconstituted wafer was then separated from the glass carrier through a laser ablation process using a 355-nm laser to determine optimal throughput. Experiments to study correlation of laser release layer with laser settings along with a demonstration of full RDL-first FOWLP integration are discussed thoroughly to address the need of throughput enhancement, which could serve as cornerstone for realizing cost-effective RDL-first FOWLP.
Process Development and Material Characteristics of TSV-less Interconnection Technology for FOWLP
(2017-01-01)
Shen, Wen-Wei
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Lin, Yu-Min
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Chang, Hsiang-Hung
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Kuo, Tzu-Ying
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Fu, Huan-Chun
Fan-out wafer-level-packaging (FO-WLP) technology is developed with the advantages of smaller package size, higher Input/Output (I/O) counts, lower cost, and better performance. In this study, the FO-WLP technology is applied to TSV-less inter-connection technology of 2.5D IC packaging and a novel RDL-first wafer level packaging is demonstrated. Firstly, a pre-coated laser release layer at the interface of RDL and carrier wafer is used for the separation of the reconfigured wafer and carrier wafer with laser de-bonding technology. Since release layer material is the key factor for de-bonding, these materials are evaluated to determine the quality. Test chips are flip-chip bonded onto a carrier wafer with 2 layers of RDL and passivation, following by wafer molding process. Wafers reveal a warp surface due to chemical material shrinkage and CTE mismatch during post mold curing. Warpage of molded wafer is needed to be optimized for equipment handling and the warpage characterization is collected to analyze by different processes. To examine the quality of the structure, electrical measurement is carried out and their respective results are presented.
Warpage Characteristics and Process Development of Through Silicon Via-Less Interconnection Technology
(2018-08-01)
Shen, Wen-Wei
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Lin, Yu-Min
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Wu, Sheng-Tsai
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Lee, Chia-Hsin
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Huang, Shin-Yi
In this study, through silicon via (TSV)-less interconnection using the fan-out wafer-level-packaging (FO-WLP) technology and a novel redistribution layer (RDL)-first wafer level packaging are investigated. Since warpage of molded wafer is a critical issue and needs to be optimized for process integration, the evaluation of the warpage issue on a 12-inch wafer using finite element analysis (FEA) at various parameters is presented. Related parameters include geometric dimension (such as chip size, chip number, chip thickness, and mold thickness), materials' selection and structure optimization. The effect of glass carriers with various coefficients of thermal expansion (CTE) is also discussed. Chips are bonded onto a 12-inch reconstituted wafer, which includes 2 RDL layers, 3 passivation layers, and micro bumps, followed by using epoxy molding compound process. Furthermore, an optical surface inspector is adopted to measure the surface profile and the results are compared with the results from simulation. In order to examine the quality of the TSV-less interconnection structure, electrical measurement is conducted and the respective results are presented.