Browsing by Author "Huang, Shuo-An"

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A 2x2-16x16 Reconfigurable GGMD Processor for MIMO Communication Systems
(2018-01-01)
Chiang, Chih-Hsuan
;
Huang, Shuo-An
;
Chen, Chiao-En
;
Yang, Chia-Hsiang
;
電子工程學系及電子研究所
The generalized geometric mean decomposition (GGMD) is a recently proposed matrix decomposition which can be viewed as a computationally efficient counterpart of the conventional geometric mean decomposition (GMD). As the GMD is the core algorithm in many high performance precoders and equalizers such as the Tomlinson-Harashima precoder and decision feedback equalizer, GGMD facilitates a more computationally efficient implementation while exhibiting identical performance. This work presents the first GGMD processor in the open literature, supporting various matrix sizes by leveraging the reconfigurable processing element (PE) using coordinate rotation digital computers (CORDICs). The implemented GGMD processor supports matrix sizes of 2(n) which ranges from 2 x 2 to 16 x 16, and the throughput performance is maximized through a PE array architecture. The chip integrates 326.9K gates in an area of 1.65 mm(2) in a 90-nm CMOS technology with the maximum throughput achieving 450K matrices/sec for a 16 x 16 matrix at 125 MHz. It dissipates 20.7-28.5 mW at 125 MHz from a 1V supply. Compared to previous GMD designs, this work supports a larger MIMO system with lower hardware complexity and power consumption.
ERROR-RESILIENT SEQUENTIAL CELLS WITH SUCCESSIVE TIME BORROWING FOR STOCHASTIC COMPUTING
(2016)
Liu, Wei-Chang
;
Chan, Ching-Da
;
Huang, Shuo-An
;
Lo, Chi-Wei
;
Yang, Chia-Hsiang
This paper presents error-resilient sequential building blocks with time-borrowing capability without extra latches and generated clocks. The circuits are able to recover the timing errors caused by PVT variations and/or over-voltage scaling by up to half a cycle. Unlike prior works, the timing errors can be recovered dynamically through successive time borrowing without stalled cycles, retaining a constant throughput. The circuit structure can be applied to both ASICs and microprocessors. The proposed sequential cells are highly compatible with current cell-based IC design flow, for both feed-forward and feedback datapaths. As a proof of concept, a design with key DSP building blocks has been verified. The results show that the performance of the DSP modules is improved by 13-15% in the worst-case operation condition, yielding a promising solution for stochastic computing under an unreliable operation condition.