Browsing by Author "Huang, T. Y."

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Characteristics of N-Type Planar Junctionless Poly-Si Thin-Film Transistors
(2012)
Lin, C. I.
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Lin, H. C.
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Huang, T. Y.
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this work, we study the electrical characteristics of planar poly-Si junctionless (JL) thin-film transistors (TFTs) with 10 nm-thick channel and various gate width. The output current of JL devices is drastically larger than that of the control device with an undoped channel, owing to the abundant carriers contained in the channel of the JL devices which tends to reduce both channel and source/drain series resistances. Subthreshold swing of the JL devices is found to be larger than the control ones, owing to the existence of a depletion layer in the channel. Nonetheless, excellent on/off current ratio (>10(7)) is achieved, thanks to the use of the ultra-thin channel.
Impacts of NH(3) plasma treatment on double-gated poly-Si nanowire thin-film transistors
(2007)
Lee, K. H.
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Lin, H. C.
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Hsu, H. H.
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Huang, T. Y.
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電子工程學系及電子研究所
NH(3) plasma treatment has been employed to improve the performance of a novel double-gated poly-Si nanowire thin-film transistor in terms of increased on-state current, reduced off-state current, and steeper sub-threshold slope. An interesting finding is that the radiation damage, accompanying by a negative shift in threshold voltage, appears to occur in the early stage of plasma treatment for devices with top poly-gate. Such effect disappears when an Al top-gate is used instead.
Operations of poly-Si nanowire thin-film transistors with a multiple-gated configuration
(2007-05-30)
Su, C. J.
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Lin, H. C.
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Tsai, H. H.
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Hsu, H. H.
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Wang, T. M.
In this study, a novel multiple-gated (MG) thin-film transistor (TFT) with poly-Si nanowire ( NW) channels is fabricated using a simple process flow. In the proposed new transistors, poly-Si NWs were formed in a self-aligned manner and were precisely positioned with respect to the source/drain, and the side-gate. Moreover, the NW channels are surrounded by three gates, i.e., top-gate, side-gate and bottom-gate, resulting in much stronger gate controllability over the NW channels, and greatly enhanced device performance over the conventional single-gated TFTs. Furthermore, the independently applied top-gate and/or bottom-gate biases could be utilized to adjust the threshold voltage of NW channels in a reliable manner, making the scheme suitable for practical applications.
Stability of High Performance p-type SnO TFTs
(2015)
Zhong, C. W.
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Tsai, H. Y.
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Lin, H. C.
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Liu, K. C.
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Huang, T. Y.
High performance p-type SnO TFTs were fabricated and characterized in this work. Owing to thermal oxygen annealing process, the originally tin-rich oxide film was transformed into a polycrystalline SnO, resulting in decent field-effect mobility and high on/off current ratio. Electrical stability was evaluated by examining the threshold voltage shift under negative bias stresses at different stress times. A scenario considering the passivation/de-passivation of acceptor defects in the channel and the hole trapping of the gate oxide is proposed to explain the observed instability of the SnO TFTs.