Browsing by Author "Huang, Tzu-Chi"

Now showing 1 - 18 of 18

120% Harvesting Energy Improvement by Maximum Power Extracting Control for High Sustainability Magnetic Power Monitoring and Harvesting System
(2015-04-01)
Huang, Tzu-Chi
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Du, Ming-Jhe
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Kang, Yu-Chai
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Peng, Ruei-Hong
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Chen, Ke-Horng
The magnetic energy harvesting (MEH) circuit and the power monitoring system are proposed in this paper to enlarge the system sustainability on wireless sensing or the monitoring system. The proposed MEH circuit harvests magnetic power on power wires through a power sensing current transformer (CT) and charges power monitoring system. The MEH circuit includes the direct ac-dc rectifier and the maximum power extracting (MPE) control circuit. The direct ac-dc rectifier can directly rectify ac input to the dc output current. The proposed MPE control fits the characteristic of magnetic energy source compared to the conventional resistor emulation maximum power point tracking method. Owing to continuous tracking the maximum power of the CT, 120% harvesting power improvement can be achieved under the same CT\'s sensing current. Peak efficiency of 82% can be achieved under the sensing current of 8 A. The test chip is fabricated in 0.25 mu m CMOS process with an active area of 0.98 mm(2).
A 80V Output Voltage Boost Converter with Low Voltage Ripple for Avalanche Photodiode(APD)
(2011)
Yang, Yao-Yi
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Hsieh, Chun-Yu
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Huang, Tzu-Chi
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Lee, Yu-Huei
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Wang, Shih-Wei
The Avalanche Photodiodes (APDs) are widely used in a variety of optical application requiring high sensitivity, such as long-distance optical communication and optical distance measurement, because the APDs can detect the low level light. APDs accompanied with the Transimpedance Amplifier (TIA) are utilized on the receiver side in the communication system. The trend of integrating the active optical components faces the challenge of integrating different voltage levels. In general, the operation voltage of TIA is usually 1.8 V or 3.3 V. However, the APD requires a high reverse-biasing voltage of 40 V - 80 V. Therefore, a high conversation-ratio boost converter must be included to provide the high voltage to bias the APD. Besides, output voltage ripple must be minimized to decrease the influence on communication signals. Experimental results show the 80 V output voltage boosted from the input voltage of 2.5 V. The output voltage ripple is 2 mV under the condition of 1 mA load current.
A Battery-Free 217 nW Static Control Power Buck Converter for Wireless RF Energy Harvesting With alpha-Calibrated Dynamic On/Off Time and Adaptive Phase Lead Control
(2012-04-01)
Huang, Tzu-Chi
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Hsieh, Chun-Yu
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Yang, Yao-Yi
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Lee, Yu-Huei
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Kang, Yu-Chai
Abattery-free nano-power buck converter with a proposed dynamic on/off time (DOOT) control can achieve high conversion efficiency over a wide load range. The DOOT control can predict the on/off time at different input voltages without a power consuming zero current detection (ZCD) circuit, as well as suppress static power in idle periods. To adapt to the fluctuations in a harvesting system, the proposed alpha-calibration scheme guarantees accurate ZCD over process, voltage variation, and temperature (PVT) in the DOOT to improve power conversion efficiency. Furthermore, the adaptive phase lead (APL) mechanism can improve inherent propagation delay attributable to low-power and non-ideal comparator, thus improving load regulation by a maximum of 30 mV. The test chip was implemented in 0.25-mu m CMOS process with a die area of 0.39 mm(2). Experimental results showed 95% peak efficiency, low static power of 217 nW and good load regulation of 0.1 mV/mA, which are suitable for RF energy harvesting applications.
A Direct AC-DC and DC-DC Cross-Source Energy Harvesting Circuit with Analog Iterating-Based MPPT Technique with 72.5% Conversion Efficiency and 94.6% Tracking Efficiency
(2016-08)
Chen, Shin-Hao
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Huang, Tzu-Chi
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Ng, Shao Siang
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Lin, Kuei-Liang
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Du, Ming-Jhe
The proposed cross-source energy (CSE) harvesting system accepts universal energy sources, including the ac and dc sources. The buck-boost conversion of CSE automatically converts ac or dc input into dc output without being limited by the type of universal energy source. The CSE technique simultaneously supplies the regulated output for the system loading and the battery charging output. A test chip fabricated in the VIS Bipolar, CMOS, and DMOS (BCD) process can optimally derive harvest energy with 72.5% power efficiency when one solar input source is used. A backup converter is designed to complement the CSE technique to guarantee the regulation of output voltage. The proposed analog iterating-based (AIB) maximum power point tracking (MPPT) technique achieves 94.6% tracking efficiency without complex data calculation and storage, which are better results compared with those of previous research.
A Photovoltaic System with Analog Maximum Power Point Tracking and Grid-Synchronous Control
(2012)
Huang, Tzu-Chi
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Lee, Yu-Huei
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Du, Ming-Jhe
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Hsieh, Chun-Yu
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Yang, Chih-Yu
A low cost maximum power point tracking (MPPT) technique is proposed in this paper for high power efficiency in photovoltaic systems to track the maximum power point (MPP). Compared to the various studies of the MPPT topologies, the proposed implementation is achieved by monitoring the power slope conditions of solar panels. The post grid-connected DC-AC inverter helps feedback the transformative power for providing AC power. Experiment results demonstrate the rapid tracking operation of MPP and a high tracking effectiveness of 97.3%.
A Single-Inductor Bipolar-Output Converter with 5 mV Positive Voltage Ripple for Active Matrix OLED
(2011)
Chen, Wei-Chung
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Chiu, Chao-Chang
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Hsieh, Chun-Yu
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Huang, Tzu-Chi
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Lee, Yu-Huei
This paper proposed a single inductor bipolar outputs (SIBO) switching converter for the active matrix Organic Light-Emitting Diode (AMOLED). The negative voltage is generated by the inverting buck-boost converter, which is regulated by the high signal-to-noise ratio comparator. Moreover, the boost converter is utilized to provide the positive output voltage. The proposed switching converter uses the switch sequential to reduce the positive voltage ripple to about 5 mV with the proportional-integral (PI) compensator to guarantee good line and load-regulation. Simulation results show the positive output voltage is regulated to 5V and the negative output voltage is -7V for driving the AMOLED. When the load current is 25 mA and the ESR is 30m Omega, the output voltage ripples are equal to 5 mV and 11 mV for positive and negative voltages, respectively. Besides, the load and line regulations of positive output voltage are 0.24 mV/mA and 5 mV/V, respectively. The maximum efficiency is 88.5% when the input voltage is 4.5 V and the load current is 50mA
A Switchable Digital-Analog Low-Dropout Regulator for Analog Dynamic Voltage Scaling Technique
(2014-03-01)
Chen, Wei-Chung
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Ping, Su-Yi
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Huang, Tzu-Chi
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Lee, Yu-Huei
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Chen, Ke-Horng
Dual dynamic voltage scaling (DVS) techniques employed in single-inductor dual-output (SIDO) converters are used to improve the efficiency of the system-on-a-chip (SoC). One DVS technique for digital circuits is controlled by the SoC processor. This paper presents the analog DVS (ADVS) technique for analog circuits to scale voltage across the power MOSFET of the switchable digital-analog (D/A) low-dropout (LDO) regulator which is the post-regulator cascaded in series with the SIDO converter. The ADVS determines the tradeoff between voltage suppression and efficiency. Furthermore, because of the digital operation of the D/A LDO regulator, the quiescent current is further reduced at light loads while the load current requirement is minimized. In addition, the limitation of the capacitor-free LDO is significantly reduced by a few microamperes. The test chip was fabricated using a 40-nm CMOS process. Experimental results demonstrated switchable D/A LDO regulator operation with peak efficiency at 96.7% in analog operation and a 5-mV output voltage ripple at 120-mA load resulting from the advantage of ripple suppression. The power efficiency could be sustained at a value over 92.57% even when the load current decreased to 1 mu A.
All Digital Phase-Locked Loop Using Active Inductor Oscillator and Novel Locking Algorithm
(2011)
Huang, Tzu-Chi
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Huang, Hong-Yi
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Liu, Jen-Chieh
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Cheng, Kuo-Hsing
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Luo, Ching-Hsing
A fast locking all-digital phase-locked loop (ADPLL) with the active inductor oscillator is proposed. An LC-tank DCO with a tunable active inductor can obtain a wider operational frequency range, smaller area and higher signal quality. The proposed frequency and phase locking algorithm can achieve good jitter performance, high frequency accuracy, and low circuit complexity. The ADPLL is designed using a 0.18 um CMOS process. The operational frequency range of the ADPLL is from 318 MHz to 458 MHz. The RMS and the peak-to-peak jitters at 402 MHz are 4.2 ps and 94 ps, respectively. The core size is 390x390 um(2). The power consumption is 5.4 mW at 416 MHz.
An Embedded Dynamic Voltage Scaling (DVS) System Through 55 nm Single-Inductor Dual-Output (SIDO) Switching Converter for 12-Bit Video Digital-to-Analog Converter
(2012-07-01)
Chou, Wen-Shen
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Huang, Tzu-Chi
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Lee, Yu-Huei
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Yang, Yao-Yi
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Su, Yi-Ping
"This paper proposes a 55 nm CMOS 12-bit current- steering video digital-to-analog converter (DAC) directly powered by the single-inductor dual-output (SIDO) switching converter to compose a dynamic voltage scaling (DVS) system and improve the power efficiency. Dual-DVS control in both digital and analog circuits can effectively reduce power consumption. With various supply voltages, the video DAC can meet several different specifications in the power optimized (PO) mode. Furthermore, for DAC, the proposed 3S method, including finger separating, splitting and shifting, achieves good differential nonlinearity (DNL) performance to 0.78/0.4 least significant bit (LSB) and integral nonlinearity (INL) 1.3/1.0 LSB (with/without SIDO converter) without additional calibration. It also suppresses the switching noise interference from the SIDO converter. Moreover, for SIDO converter, the cross-regulation performance is greatly improved in both transient and steady state to achieve lowest interference for the analog supply. The total power efficiency can be improved up to 11.5% and 28% in the DVS and the PO mode. The SIDO supplied DAC with the dual-DVS function achieves 69.88 dB spurious free dynamic range (SFDR) at the 1 V output swing and 1 MHz input. The proposed intrinsic 12-bit DAC and SIDO converter achieve high definition video DAC performance with the benefit of area and energy efficiency."
Embedded Single-Inductor Bipolar-Output DC-DC Converter in Class-D Amplifier for Low Common Noise
(2016-04-01)
Chen, Shin-Hao
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Lin, Kuei-Liang
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Ng, Shao Siang
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Huang, Tzu-Chi
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Chen, Ke-Horng
This paper proposes a high efficiency class-D amplifier (CDA) with embedded single-inductor bipolar output (SIBO) power module. The characteristics of SIBO converter\'s bipolar outputs not only suppress equivalent common-mode noise but also remove several large external bulky components in conventional boost supply CDA systems. Since bipolar outputs in the SIBO provide independent driving capability, CDA is capable of operating in both single-ended and bridge-tide load configurations. Furthermore, the proposed dynamic voltage boosting technique adjusts the SIBO output voltage level according to the CDA\'s output level with 5% power efficiency improvement. Peak total harmonic distortion plus noise performance is 0.012%. Peak power efficiency of SIBO and CDA is 89% and 93.2%, respectively.
Fast Charging and High Efficiency Switching-Based Charger With Continuous Built-In Resistance Detection and Automatic Energy Deliver Control for Portable Electronics
(2014-07-01)
Huang, Tzu-Chi
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Peng, Ruei-Hong
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Tsai, Tsu-Wei
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Chen, Ke-Horng
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Wey, Chin-Long
The continuous built-in resistance detection (CBIRD) is proposed in the switching-based charger system to achieve fast charging. Corresponding to built-in resistance (BIR) variation of Li-ion battery and charging current limitation from input energy, the CBIRD dynamically adjusts the transition voltage at the constant current (CC) mode. As a result, the transition timing from CC mode to the constant voltage (CV) mode can be postponed. Rated large charging current and extended period in CC mode effectively reduce charging time. Besides, the proposed automatic energy deliver control (AEDC) technique considers both loading system and battery status simultaneously to manage charging current according to the loading system\'s requirement and input supply energy for high efficiency charging. The proposed switching-based charger system was fabricated in 0.25 m CMOS process and occupied 3 mm(2) silicon area. The charger system can save up to 40% of charging time. The charger system achieves 87% of peak power efficiency at a rated 1 A charging current.
Instruction-Cycle-Based Dynamic Voltage Scaling Power Management for Low-Power Digital Signal Processor With 53% Power Savings
(2013-11-01)
Peng, Shen-Yu
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Huang, Tzu-Chi
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Lee, Yu-Huei
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Chiu, Chao-Chang
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Chen, Ke-Horng
This paper presents and analyzes a fully digital instruction-cycle-based dynamic voltage scaling (iDVS) power management strategy for low-power processor designs. The proposed iDVS technique is fully compatible with conventional DVS scheduler algorithms. An additional computer aided design-based design flow was embedded in a standard cell library to implement the iDVS-based processor in highly integrated system-on-a-chip applications. The lattice asynchronous self-timed control digital low-dropout regulator with swift response and low quiescent current was also utilized to improve iDVS voltage transition response. Results show that the iDVS-based processor with the proposed adaptive instruction cycle control scheme can efficiently perform millions of instructions per second during iDVS transition. The iDVS-based digital signal processor chip was implemented in a HH-NEC 0.18-mu m standard complementary metal-oxide semiconductor. Measurement results show that the voltage tracking speed with 11.6 V/mu s saved 53% power.
Minimized Transient and Steady-State Cross Regulation in 55-nm CMOS Single-Inductor Dual-Output (SIDO) Step-Down DC-DC Converter
(2011-11-01)
Lee, Yu-Huei
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Huang, Tzu-Chi
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Yang, Yao-Yi
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Chou, Wen-Shen
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Chen, Ke-Horng
A single-inductor dual-output (SIDO) step-down DC-DC converter with continuous conduction mode (CCM) operation is proposed to achieve an area-efficient power management module. The low-voltage energy distribution controller (LV-EDC) can simultaneously guarantee good voltage regulation and low output voltage ripple. With the proposed dual-mode energy delivery methodology, cross regulation in steady-state output voltage ripple, which is rarely discussed, and cross regulation in load transient response are both effectively reduced. In addition, the energy mode transition operation helps obtain the appropriate energy operation mode using the energy delivery paths for dual outputs. Moreover, within the allowable output voltage ripple, the automatic energy bypass (AEB) mechanism can reduce the number of energy delivery paths, thereby ensuring voltage regulation and further enhancing efficiency. The test chip, fabricated in 55-nm CMOS, occupies 1.44 mm(2) and achieves 91% peak efficiency, low output voltage ripple, and excellent load transient response for a high-efficiency system-on-a-chip (SoC) integration.
Non-invasion Power Monitoring with 120% Harvesting Energy Improvement by Maximum Power Extracting Control for High Sustainability Power Meter System
(2012)
Huang, Tzu-Chi
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Du, Ming-Jhe
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Yang, Yao-Yi
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Lee, Yu-Huei
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Kang, Yu-Chai
Magnetic energy harvesting (MEH) circuit for system sustainability and power monitoring system with a novel dual-wire current transformer (DWCT) are proposed in this paper. MEH circuit simultaneously senses and harvests the magnetic energy. DWCT has the benefits of non-invasion measurement (NIM) and is easy to use. The designed direct AC-DC rectifier with maximum power extracting (MPE) control fits the characteristic of magnetic energy source. Thus, 120% harvesting power improvement can be achieved under the same sensing current.
Power Management With a Low-Ripple High-Conversion-Ratio 80-V Output Voltage Boost Converter for Avalanche Photodiode System
(2013-07-01)
Yang, Yao-Yi
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Wang, Shih-Wei
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Hsieh, Chun-Yu
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Huang, Tzu-Chi
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Lee, Yu-Huei
Avalanche photodiodes (APDs) accompanied with the transimpedance amplifiers (TIAs) are often utilized as receivers in the communication system. A drawback of APDs is that the avalanche gain depends on temperature and varies with the bias voltage, leading to a decrease in the quality of communication. Moreover, the bias voltage for a high avalanche gain is up to 80 V, implying that a power module is inevitably required and raises the difficulty of integration. Therefore, a power management is proposed to provide an 80-V voltage and compensates the temperature dependence for a constant avalanche gain. The low-ripple high-conversion-ratio boost converter eliminates the LC resonance resulted from the nonideal effect of diodes to supress the output voltage ripple, implying that a high quality of bias voltage is guaranteed. Experimental results show that the output voltage ripple is 2.12 mV under the condition of 1-mA load current. A 97% accuracy of avalanche gain is proved to guarantee the high quality of APDs.
Real-Time Instruction-Cycle-Based Dynamic Voltage Scaling (iDVS) Power Management for Low-Power Digital Signal Processor (DSP) with 53% Energy Savings
(2012)
Peng, Shen-Yu
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Lee, Yu-Huei
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Wu, Chun-Hsien
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Huang, Tzu-Chi
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Chen, Ke-Horng
this paper presents an instruction-cycle-based dynamic voltage scaling (iDVS) power management strategy for a low-power processor design. The iDVS technique is fully compatible with conventional DVS scheduler algorithms. Furthermore, an additional iDVS design flow embedded in the standard cell lib flow is proposed to implement the iDVS-based DSP. In addition, the fast-response bidirectional asynchronous wave-pipeline (BAWP) digital low-dropout (LDO) regulator is also presented to improve the iDVS performance. The iDVS-based DSP chip implemented in an HH-NEC 0.18 mu m standard CMOS process demonstrates 53% energy savings over that without the iDVS technique.
Single Inductor Quad Output Switching Converter with Priority-Scheduled Program for Fast Transient and Unlimited-load Range in 40nm CMOS Technology
(2014-01-01)
Chen, Wei-Chung
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Huang, Tzu-Chi
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Tsai, Tsu-Wei
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Peng, Ruei-Hong
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Lin, Kuei-Liang
System-on-a-chip (SoC) applications need multiple power supplies with low noise for analog circuits and high efficiency for digital circuits. Thus, this paper proposes the priority-scheduled program (PSP) for single inductor quad output (SIQO) switching converter to manage energy delivery for four outputs. Consequently, SIQO converter with PSP can provides fast transient response and reduce cross-regulation. Besides, the level bypass detector (LBD) provides unlimited load range between each output through the shared inductor. The PSP cooperates with the LDB to transfer energy to low priority outputs to avoid overshoot at high priority outputs. With the two low-dropout regulator (LDR) working as buffers at low priority outputs, voltage disturbance can be filtered out. The SIQO converter fabricated in 40nm CMOS technology satisfies power requirements in portable electronics with 0.2% low noise, 15 mu s fast transient response, and cross-regulation smaller than 30mV.
Single-Inductor Quad-Output Switching Converter With Priority-Scheduled Program for Fast Transient Response and Unlimited Load Range in 40 nm CMOS Technology
(2015-07-01)
Chen, Wei-Chung
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Su, Yi-Ping
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Huang, Tzu-Chi
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Tsai, Tsu-Wei
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Peng, Ruei-Hong
System-on-a-chip (SoC) applications require multiple power supply voltages with the features of low noise for analog circuits and high efficiency for digital circuits. Thus, this paper proposes the priority-scheduled program (PSP) for the single-inductor quad-output (SIQO) switching converter. This technique manages energy delivery to multiple outputs, facilitates fast transient response, and reduces cross-regulation simultaneously. Moreover, a level bypass detector (LBD) is used to overcome the limitation of significant loading differences among quad outputs in conventional designs because the PSP technique cantransfer additional energy to low-priority outputs to avoid overshoot voltage at high-priority outputs. Furthermore, voltage disturbance can be filtered out using two additional low-dropout regulators that operate as buffers cascaded at two low-priority outputs. Therefore, the SIQO converter that is fabricated in 40 nm CMOS technology satisfies the power requirements in portable electronics given its low cross-regulation of 0.2%, fast transient response of 15 mu s, and an output voltage ripple that is smaller than 30 mV.