Browsing by Author "Huang, Tzu-Hsuan"

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Predicting Vt Variation and Static IR Drop of Ring Oscillators Using Model-Fitting Techniques
(2017-01-01)
Huang, Tzu-Hsuan
;
Hung, Wei-Tse
;
Yang, Hao-Yu
;
Chang, Wen-Hsiang
;
Chen, Ying-Yen
This paper presents a statistical model-fitting framework to efficiently decompose the impact of device Vt variation and power-network IR drop from the measured ring-oscillator frequencies without adding any extra circuitry to the original ring oscillators. The framework applies Gaussian process regression as its core model-fitting technique and stepwise regression as a preprocess to select significant predictor features. The experiments conducted based on the SPICE simulation of an industrial 28nm technology demonstrate that our framework can simultaneously predict the NMOS Vt, PMOS Vt and static IR drop of the ring oscillators based on their frequencies measured at different external supply voltages. The final resulting R squares of the predicted features are all more than 99.93%.
Random Pattern Generation for Post-Silicon Validation of DDR3 SDRAM
(2015)
Yang, Hao-Yu
;
Kuo, Shih-Hua
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Huang, Tzu-Hsuan
;
Chen, Chi-Hung
;
Lin, Chris
Due to the demand of pursuing a main memory with larger data bandwidth, higher data density, and lower power, the specification of DRAM has been constantly evolved in the past decade. The new DRAM specifications support multiple operating modes with multiple timing settings. It then becomes computationally infeasible to exhaustively validate all the combinations of different operating modes, timing settings and address/data with pure simulation before silicon. In this paper, we propose a framework to generate proper random patterns for validating a newly designed DDR3 SDRAM based on its first silicon chips. The proposed framework needs to not only guarantee the correctness of the generated patterns according to the state diagram and timing constraints defined in the specification but also provide the flexibility of exploring various design corners for the targeted DDR3 SDRAM. We will also show some successful silicon-validation cases of applying the proposed framework to identify the design errors based on real DDR3 SDRAM products.