Browsing by Author "Huang, Y. -C."

Now showing 1 - 7 of 7

A new apparatus of infrared videopupillography for monitoring pupil size
(2013-01-01)
Ko, M. -L.
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Huang, T. -W.
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Chen, Y. -Y.
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Sone, B. -S.
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Huang, Y. -C.
Glaucoma was diagnosed or tracked by the intraocular pressure (IOP) generally because it is one of the physiology parameters that are associated with glaucoma. But measurement of IOP is not easy and consistence under different measure conditions. An infrared videopupillography is apparatus to monitor the pupil size in an attempt to bypass the direct IOP measurement. This paper propose an infrared videopupillography to monitoring the pupil size of different light stimulus in dark room. The portable infrared videopupillography contains a camera, a beam splitter, the visible-light LEDs for stimulating the eyes, and the infrared LEDs for lighting the eyes. It is lighter and smaller than the present product. It can modulate for different locations of different eyes, and can be mounted on any eyeglass frame. An analysis program of pupil size can evaluate the pupil diameter by image correlation. In our experiments, the eye diameter curves were not smooth and jagged. It caused by the light spots, lone eyelashes, and blink. In the future, we will improve the analysis program of pupil size and seek the approach to solve the LED light spots. And we hope this infrared videopupillography proposed in this paper can be a measuring platform to explore the relations between the different diseases and pupil response.
A Self Produced Mother Wavelet Feature Extraction Method for Motor Imagery Brain-Computer Interface
(2013)
Yeh, W. -L.
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Huang, Y. -C.
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Chiou, J. -H.
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Duann, J. -R.
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Chiou, J. -C.
Motor imagery base brain-computer interface (BCI) is an appropriate solution for stroke patient to rehabilitate and communicate with external world. For such applications speculating whether the subjects are doing motor imagery is our primary mission. So the problem turns into how to precisely classify the two tasks, motor imagery and idle state, by using the subjects\' electroencephalographic (EEG) signals. Feature extraction is a factor that significantly affects the classification result. Based on the concept of Continuous Wavelet Transform, we proposed a wavelet-liked feature extraction method for motor imagery discrimination. And to compensate the problem that the feature varies between subjects, we use the subjects\' own EEG signals as the mother wavelet. After determining the feature vector, we choose Bayes linear discriminant analysis (LDA) as our classifier. The BCI competition III dataset IVa is used to evaluate the classification performance. Comparing with variance and fast Fourier transform (FFT) methods in feature extraction, 2.02% and 16.96% improvement in classification accuracy are obtained in this work respectively.
First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications
(2019-01-01)
Chang, S. -W.
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Sung, P. -J.
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Chu, T-Y.
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Lu, D. D.
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Wang, C. -J.
For the first time, CMOS inverters and 6T-SRAM cells based on vertically stacked gate-all-around complementary FETs (CFETs) are experimentally demonstrated. Manufacturing difficulties of vertically stacked source and drain electrodes of the CFETs have been overcome by using junctionless transistors, thereby reducing the number of lithographic steps required. Furthermore, with post metallization treatments, both the voltage transfer characteristics (VTCs) of CMOS inverters and butterfly curves of SRAM show significant improvements due to the symmetry of nMOS and pMOS threshold voltages. Simulation shows that 3-dimensional CFET inverters have lower input parasitic capacitance than standard 2-dimensional CMOS, leading to reduced gate delay and lower power consumption.
Ge FinFET CMOS Inverters With Improved Channel Surface Roughness by Using In-Situ ALD Digital O-3 Treatment
(2018-01-01)
Yeh, M. -S.
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Luo, G. -L.
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Hou, F. -J.
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Sung, P. -J.
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Wang, C. -J.
Improved electrical characteristics of CMOS inverters composed of Ge n- and p-finFETs were demonstrated by utilizing newly introduced Ge surface treatments. In-situ digital O-3 treatment in ALD chamber was adopted on the surface of Ge fin sidewall in order to reduce the roughness and etching damages through the GeO desorption mechanism. The treatment effects were checked by AFM and C-V measurements. By combining this treatment with optimized microwave annealing, sub-threshold slope and the I-ON/I-OFF ratio were remarkably improved in both n-finFET and p-finFET, and Ge CMOS inverters with high voltage gain of 50.3 V/V at low V-D = 0.6 V was realized. Finally, simulations on an ideal Ge CMOS inverter were presented.
Ge Nanowire FETs with HfZrOx Ferroelectric Gate Stack Exhibiting SS of Sub-60 mV/dec and Biasing Effects on Ferroelectric Reliability
(2017-01-01)
Su, C. -J.
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Hong, T. -C.
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Tsou, Y. -C.
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Hou, F. -J.
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Sung, P. -J.
Ge nanowire (NW) FETs exhibiting subthreshold swing (SS) of 54 mV/dec at room temperature are demonstrated with ferroelectric HfZrOx (FE-HZO) gate stack for the first time. I-ON/I-OFF ratios higher than 10(7) and 10(6) for p- and n-NWFETs, respectively, have been achieved by adopting the gate-all-around (GAA) configuration. Electrical biasing effects on the HZO ferroelectric reliability have been systematically investigated in this work. It is found that the polarization behavior will degrade with electrical stress time and can be recovered. The Ge HZO FinFET CMOS inverter shows experimentally voltage gain of 24.8 V/V.
Improvement on CDM ESD Robustness of High-Voltage Tolerant nLDMOS SCR Devices by Using Differential Doped Gate
(2014)
Chen, S. -H.
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Linten, D.
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Scholz, M.
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Hellings, G.
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Boschke, R.
Early failure has been observed during CDM ESD stress on high-voltage tolerant nLDMOS-SCR devices in a standard low-voltage CMOS technology due to the gate oxide (GOX) degradation. In this work, we propose a special p+/n+ differential doped gate which boosts the CDM ESD failure current level with a factor of 3 to 9.
Voltage Transfer Characteristic Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs applications
(2018-01-01)
Sung, P. -J.
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Chang, C. -Y.
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Chen, L. -Y.
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Kao, K. -H.
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Su, C. -J.
For the first time, CMOS inverters with different numbers of vertically stacked junctionless (JL) nanosheets (NSs) are demonstrated. All fabrication steps were below 600 degrees C, and 8-nm thick poly-Si NSs with smooth surface roughness were formed by a dry etching process. Compared to single channel devices, stacked n/p-channel FETs exhibit higher on-current with low leakage current. Furthermore, a common-gate process was performed for the fabrication of CMOS inverters. By adjusting the NS layer numbers for n/pFETs, respectively, the voltage transfer characteristics (VTCs) of the CMOS inverter can be matched much better to reduce the noise margin due to on-current matching without area penalty. This work experimentally demonstrates a new configuration of CMOS inverters on stacked NSs, which is promising for System-on-Panel (SoP) and 3D-ICs applications.