Browsing by Author "Huang, Y. -F."

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Enhancing the Solubility of n-Type Diketopyrrolopyrrole-Dicyanovinyl Molecules with Hybrid Siloxane Group for Solution-Processable Organic Field-Effect Transistor
(2019-01-01)
Prakoso, S. P.
;
Ciou, G. -T.
;
Lin, H. -Y.
;
Peng, W. -C.
;
Sie, J. -H.
Diketopyrrolopyrrole (DPP) organic dye is well-known to have poor solubility in most common organic solvents. In general, flexible alkyl chain is used to enhance the solubility of conjugated small molecules by disrupting the attraction between molecules. In this study, we have integrated hybrid organic-inorganic siloxane group as a solubilizing agent on DPP molecule carrying dicyanovinyl (DCV) as an electron-withdrawing group. UV-Vis absorption spectra were collected to evaluate the optical properties of these compounds. The electrical performances of these organic semiconductors were examined by fabricating into transistor device with them as active channel layer in the bottom gate staggered configuration. Furthermore, the molecular packing in thin films from this series was investigated by 2D grazing incident x-ray diffraction (GIXD) in relationship with device performances. It is shown that the siloxane group at the side chain of DPP effectively enhances the solubility of this molecule compared to DPP molecule with branched alkyl chain from previous study. A better solubility allows for device fabrication by solution process yet improves crystallinity of organic films and thus its electrical device performance.
First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications
(2019-01-01)
Chang, S. -W.
;
Sung, P. -J.
;
Chu, T-Y.
;
Lu, D. D.
;
Wang, C. -J.
For the first time, CMOS inverters and 6T-SRAM cells based on vertically stacked gate-all-around complementary FETs (CFETs) are experimentally demonstrated. Manufacturing difficulties of vertically stacked source and drain electrodes of the CFETs have been overcome by using junctionless transistors, thereby reducing the number of lithographic steps required. Furthermore, with post metallization treatments, both the voltage transfer characteristics (VTCs) of CMOS inverters and butterfly curves of SRAM show significant improvements due to the symmetry of nMOS and pMOS threshold voltages. Simulation shows that 3-dimensional CFET inverters have lower input parasitic capacitance than standard 2-dimensional CMOS, leading to reduced gate delay and lower power consumption.