Browsing by Author "Huang, Yi-Jie"

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ESD Protection Design with Latchup-Free Immunity in 120V SOI Process
(2015)
Huang, Yi-Jie
;
Ker, Ming-Dou
;
Huang, Yeh-Jen
;
Tsai, Chun-Chien
;
Jou, Yeh-Ning
Electrostatic discharge (ESD) protection with lowvoltage (LV) field-oxide devices in stacked configuration are proposed for high-voltage (HV) applications in a 0.5-mu m 120V SOI process. Stacked LV field-oxide devices with different stacking numbers have been verified in silicon chip to exhibit both of high ESD robustness and latchup-free immunity for HV applications.
Investigation of Human-Body-Model and Machine-Model ESD Robustness on Stacked Low-Voltage Field-Oxide Devices for High-Voltage Applications
(2016-08)
Huang, Yi-Jie
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Electrostatic discharge (ESD) robustness of lowvoltage (LV) field-oxide devices in stacked configuration for high-voltage (HV) applications was investigated in a 0.5-mu m HV silicon on insulator (SOI) process. Stacked LV field-oxide devices with different stacking numbers have been verified in a silicon chip to exhibit both a high ESD robustness and latch-up immunity for HV applications. The effect of turn-on resistance in the stacked ESD protection device on ESD current waveform under human body model (HBM) and machine model (MM) ESD tests was studied. The resistance of stacked device has a significant impact on the ESD peak current and damping waveform, especially in MM ESD test. The MM ESD level can be increased by the numbers of LV field-oxide devices in stacked configuration, but the HBM ESD level is still kept the same. The mechanism to cause such a result has been theoretically analyzed in detail in this paper.