Browsing by Author "Huang, Yu-Chung"

Now showing 1 - 15 of 15

A 12-bit Multi-Channel Non-Calibrating Dual-Mode Successive Approximation ADC for Power Management Bus (PMBus) Devices
(2008)
Chiang, Cheng-Ta
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Huang, Yu-Chung
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper 12-bit multi-channel non-calibrating dual-mode successive approximation ADC for PMBus devices is newly proposed The proposed dual-mode data converter is attractive due to that all the requirements of the PMBus devices, which are high resolution, low-cost, dual-mode, multi-channel, and low power consumption for portable products, are successfully matched. Based upon the device parameters of 0.25 mu m 1P5M CMOS technology with 3.3/2.5 V power supply, all the functions and performance of the proposed dual-mode data converter for PMBus are successfully tested and proven through SPICE simulations and verified in the measurements. The area of this chip is 1.64 x 1.56 mm(2) and the measured power consumption is 1.683 in W The proposed dual-mode data converter is suitable for power monitoring systems, such as PMBus devices.
A 14-bit Oversampled Delta-Sigma Modulator for Silicon Condenser Microphones
(2009)
Chiang, Cheng-Ta
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Huang, Yu-Chung
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電機學院
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College of Electrical and Computer Engineering
In this paper, a 14-bit oversampled delta-sigma modulator for silicon condenser microphones is newly proposed. The proposed oversampled delta-sigma modulator is attractive due to that the requirements of silicon condenser microphones are successfully matched. Based upon the device parameters of 0.35 mu m 2P4M CMOS technology with 3.0 V power supply, all the functions and performance of the proposed delta-sigma modulator for silicon condenser microphones are successfully tested and proven through MATLAB in the behavior simulations and SPICE in the circuit simulations. The area of this fabricated chip is 1327 x 944 mu m(2) and the simulated power consumption is 5.25 mW. The proposed delta-sigma modulator is suitable for silicon condenser microphones applied on mobile phones. laptops, PDAs, and hearing aids, etc.
A CMOS integrated capacitance-to-frequency converter with digital compensation circuit designed for sensor interface applications
(2007)
Chiang, Cheng-Ta
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Wang, Chi-Shen
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Huang, Yu-Chung
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交大名義發表
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National Chiao Tung University
In this work, a capacitive signal conditioner of a CMOS integrated capacitance-to-frequency converter wit h digital compensation circuit designed for sensor interface applications is newly proposed. The proposed converter has the low cost feature. That is due to that the output signal of the proposed converter is a digitized signal produced without realizing the analog to digital converter. Hence, the hardware cost could be reduced. Besides, the output of the proposed converter is a pulse stream, it could be easily sent over a wide range of transmission media, such as PSN, radio, optical, K ultrasonic, and etc. Based upon 0.35 um 2P4M CMOS technology, measurement results have successfully verified the correct functions and performance of the integrated capacitance-to-frequency converter with digital compensation circuit designed for sensor interface applications. The area of this fabricated chip is 940 x 1080 um 2 and the power consumption is 6.4 mW. The proposed converter is not only suitable for capacitive measurement systems, but also applications of demanding wide dynamic output frequency range.
A CMOS Phase to Digital Converter for Optical Encoders
(2011-01-01)
Chiang, Cheng-Ta
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Hsieh, Kaun-Chun
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Huang, Yu-Chung
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電機學院
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College of Electrical and Computer Engineering
In this paper, a CMOS phase to digital converter for optical encoders is newly proposed. This chip adopts a proposed phase-shift method to easily generate phase shifts of signals by using a resistor chain. Different to PLL-based and ADC-based interpolation, the complexity and hardware cost can be relaxed in this proposed chip. Based upon the device parameters of 0.5 mu m 2P2M CMOS technology with 5 V power supply, all the functions and performance of the proposed CMOS phase to digital converter for optical encoders are successfully tested and proven through SPICE simulations. The physical layout of interpolation circuits and current to voltage converter are 1000 x 600 mu m(2) and 850 x 760 mu m(2), respectively. The proposed chip is suitable for optical encoders.
A CMOS Phase to Digital Transducer for Optical Incremental Sensors
(2011-01-01)
Chiang, Cheng-Ta
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Hsieh, Kaun-Chun
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Huang, Yu-Chung
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電機學院
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College of Electrical and Computer Engineering
In this paper, a CMOS phase to digital transducer for optical incremental sensors is newly proposed. This chip adopts a proposed phase-shift method to easily generate phase shifts of signals by using a resistor chain. Different to PLL-based and ADC-based interpolation, the complexity and hardware cost can be relaxed in this proposed chip. Based upon the device parameters of 0.5 mu m 2P2M CMOS technology with 5 V power supply, all the functions and performance of the proposed CMOS phase to digital transducer for optical incremental sensors are successfully tested and proven through measurements. The physical layout including ESD I/O pads is 2010 x 1500 mu m(2). The proposed chip is suitable for optical incremental sensors.
A low-cost CMOS dual-mode AC/DC data converter for signal measuring technique
(2010-05-01)
Chiang, Cheng-Ta
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Kao, Li-Lung
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Huang, Yu-Chung
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電機工程學系
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Department of Electrical and Computer Engineering
A low-cost CMOS dual-mode AC/DC data converter for signal measuring technique is newly proposed. Instead of traditional full wave rectification, the realized synchronous rectification circuit is more attractive due to the easier integration and lower cost. In this paper, the design strategies of implementing the signal processing of AC and DC modes in the integrated circuit are discussed completely. Proven through SIMULINK in system level and SPICE simulations in circuit level, simulation results show that the proposed dual-mode AC/DC data converter achieves 8-bit resolution in DC mode and 7-bit resolution in AC mode. Measurement results have successfully verified the correct functions and performance of the proposed data converter and confirmed it for AC/DC signal measuring technique. The area of this chip is 710 x 630 mu m(2) and the measured power consumption is 5.1 mW. The proposed dual-mode AC/DC data converter is suitable for the system of analog and mixed-signal boundary scan.
A Low-Cost CMOS Integrated Dual-Mode Dual-Slope ADC with Synchronous Rectification Circuit for AC/DC Signal Measuring
(2008)
Chiang, Cheng-Ta
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Ka, Li-Lung
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Huang, Yu-Chung
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A lost-cost CMOS integrated dual-mode dual-slope ADC with synchronous rectification circuit for AC/DC signal measuring is newly proposed. Instead of traditional full wave rectifier, an improved synchronous rectifier is implemented. To realize the simplified architecture, we use only one comparator, one OP, and switches. The advantage is that it could not only support wider bandwidth for AC signal measurements from 60 Hz to 100.2 kHz, but also provide DC signals\' digitization. It could be realized by even fewer chip area where by this dual-mode dual-slope ADC is realized in a 0.25-um 1p5m; CMOS technology with a chip area 710 x 630 mu m(2). Simulation results show that ADC achieves 8-bit resolution in DC mode and 7-bit resolution in AC mode with 100 kHz signal bandwidth. Total power consumption is 5 mW
A Monolithic CMOS Autocompensated Sensor Transducer for Capacitive Measuring Systems
(2008-11-01)
Chiang, Cheng-Ta
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Wang, Chi-Shen
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Huang, Yu-Chung
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a monolithic complimentary metaloxide-semiconductor (CMOS) autocompensated sensor transducer for capacitive measuring systems is newly presented. The proposed converter is compact and robust to integrate in capacitive measuring systems. The proposed autocompensated sensor transducer is attractive due to the fact that a digitized signal is produced without realizing the analog-to-digital converter. Hence, the hardware cost could be reduced. Furthermore, the output signal of the proposed transducer is a pulse stream; it could be easily sent over a wide range of transmission media, such as package switch networks (PSNs), radios, and optical, infrared (IR), and ultrasonic media. Another innovation is that the proposed automatic compensation circuits enhance and compensate the linear relation between the variable capacitance of the detected sensor and the output digital frequency over a wide dynamic frequency range. Measurement results have successfully verified the functions and the performance of the proposed autocompensated sensor transducer and confirmed that it is possible to apply it to the air pressure sensor. The area of this chip is 940 x 1080 mu m(2) and the power consumption is 6.4 mW. The proposed transducer is not only suitable for capacitive measuring systems but also practical for application in the front-end systems of the wireless sensor network.
A semi-cylindrical capacitive sensor with interface circuit using for fluidic measuring
(2006)
Chiang, Cheng-Ta
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Huang, Yu-Chung
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, a send-cylindrical capacitive sensor with interface circuit using for fluidic measuring is newly proposed. The numerical analysis method to calculate the capacitance of the semi-cylindrical capacitive sensor is analyzed and discussed. Besides, the interface circuit is compact to simplify the circuit complexity, and could be easily implemented for fluidic measuring. The pF-range capacitive variation of the send-cylindrical capacitive sensor can be detected and converted into voltage variation by the interface circuit. All the functions of the interface circuit are proved successfully through HSPICE simulation. These simulation results have successfully confirmed the correct functions and performance of the send-cylindrical capacitive sensor with interface circuit using for fluidic measuring.
A semi-cylindrical capacitive sensor with signal conditioner for flow meter applications
(2006)
Chiang, Cheng-Ta
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Huang, Yu-Chung
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a semi-cylindrical capacitive sensor with signal conditioner for flow meter applications is newly proposed. The numerical analysis method to calculate the capacitance of the semi-cylindrical capacitive sensor is analyzed and discussed. The pF-range capacitive variation of the semi-cylindrical capacitive sensor can be detected and converted into voltage variation by the signal conditioner. Besides, the signal conditioner is compact to simplify the circuit complexity, and could be easily implemented for flow meter applications. All the functions of the signal conditioner for flow meter applications are tested and proved through HSPICE simulation. Measurement results have successfully confirmed the correct functions and performance of the semi-cylindrical capacitive sensor with signal conditioner for flow meter applications, which ranges from 0.136 to 4.746 L/min, on the LCD panel coating machine.
A semicylindrical capacitive sensor with interface circuit used for flow rate measurement
(2006-12-01)
Chiang, Cheng-Ta
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Huang, Yu-Chung
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, a semicylindrical capacitive sensor with an interface circuit used for flow rate measurement is proposed. The numerical analysis method to calculate the capacitance of the semicylindrical capacitive sensor is analyzed and discussed. The picofarad-range capacitive variation of the semicylindrical capacitive sensor can be detected and converted into voltage variation by the interface circuit. Besides, the interface circuit is compact enough to simplify the circuit complexity and could be easily implemented for flow rate measurement. All the functions of the capacitive sensing method of the semicylindrical capacitive sensor used for flow rate measurement are proved successfully through HSPICE simulation. Measurement results have successfully confirmed the correct functions and performance of the semicylindrical capacitive sensor with an interface circuit used for flow rate measurement, which ranges from 0.136 to 4.746 L/min, on the liquid crystal display panel coating machine.
An Automatic Light Monitoring System with Light-to-Frequency Converter for Flower Planting
(2008)
Kuo, Wei-Cheng
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Chiang, Cheng-Tai
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Huang, Yu-Chung
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, an automatic light monitoring system with light-to-frequency converter for flower planting is newly proposed. Based on the requirements for flower planting, the proposed light monitoring system is thus analyzed and designed. Besides, the designed light transducer which is implemented as a light-to-frequency converter, is attractive due to that a digitized signal is produced without realizing the analog to digital converter Hence, the hardware cost could be reduced. All the functions and performance of the proposed light monitoring system are successfully proven through measurement results. The proposed light monitoring system is rather suitable for the needs in a large flower planting area.
Design of a CMOS Led Print Head Driver With Compensation Circuits
(2012-05-01)
Chiang, Cheng-Ta
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Kuo, Chun-Ting
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Huang, Yu-Chung
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交大名義發表
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National Chiao Tung University
In this paper, a CMOS LED print head driver with compensation circuits is newly proposed. Due to the process and fabrication variations, two compensation circuits are proposed. One is to perform the chip compensation, and the other is to do the pixel compensation. Besides, a method of a single-chip segment exposure is also proposed to make the power consumption more efficient. Based upon the device parameters of 0.5 mu m 1P2M CMOS technology with 3.3 V power supply, all the functions and performance of the proposed CMOS LED print head driver with compensation circuits are successfully tested and proven through measurements. The area including ESD I/O pads is 2000 x 2000 mu m(2). The proposed chip is suitable for LED printers.
Design of a CMOS phase to digital transducer for optical incremental sensors
(2011-11-01)
Chiang, Cheng-Ta
;
Hsieh, Kaun-Chun
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Huang, Yu-Chung
;
電機學院
;
College of Electrical and Computer Engineering
In this paper, a CMOS phase to digital transducer for optical incremental sensors is newly proposed. The proposed chip can easily produce phase shifts of signals by using a resistor chain. A set of calibration circuits for optical incremental sensors is also designed in the proposed chip. Another innovation is that the outputs of the proposed chip are directly digitized; they could be easily sent over a wide range of transmission media, such as PSN, radio, optical, IR, ultrasonic, etc. Besides, it does not also need a ROM component or a fast counter as used in the structures of ADC-based and PLL-based interpolations. Based upon the device parameters of 0.5 mu m 2P2M CMOS technology with 5 V power supply, all the functions and performance of the proposed CMOS phase to digital transducer for optical incremental sensors are successfully tested and proven through measurements. The area of the proposed chip including ESD I/O pads is 2010 x 1502 mu m(2). The interpolation factor is 5, 10, and 40. The proposed chip is suitable for optical incremental sensors. (C) 2011 Elsevier B.V. All rights reserved.
Optimal and heuristic algorithms for all-optical group multicast in resource-constrained WDM networks
(2016-10)
Yang, Wen-Lin
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Yang, Chun-Tao
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Huang, Yu-Chung
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電機學院
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College of Electrical and Computer Engineering
Given a sparse-splitting wavelength-division multiplexing network with no wavelength converter, we study a group multicast problem that is how to transmit a number of multicast streams from the video server to multiple destinations simultaneously. To avoid the situation that the wavelengths are used up by the first few requests, one wavelength is available for each multicast request. Hence, some of destinations may not be included in the multicast trees because of the lack of wavelengths. Our goal is to construct a number of light trees with conflict-free wavelengths for multiple requests so that the number of served clients is maximized. This problem is named as the revenue-maximized and delay-constrained group multicast routing problem. We first determine a set of multicast trees with the maximum number of served clients, then followed by the wavelength assignment to allocate the minimum number of wavelengths to the resulting trees. In this study, we propose two Integer Linear Programming ILP-based algorithms for determining the optimal solutions for the light-tree construction problem and the wavelength assignment problem, respectively. For large-scale networks, two heuristics are introduced to solve the light-tree construction problem approximately. A set of simulations are also provided for comparing performances of our algorithms against the other published methods. Copyright (c) 2016 John Wiley & Sons, Ltd.