Browsing by Author "Huang, Yu-De"

Now showing 1 - 7 of 7

A 16 Channel Real-Time EEG Processing Based on ORICA Algorithm using 28nm CMOS Technology
(2018-01-01)
Wang, Kai-Yen
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Ho, Yun-Lung
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Huang, Yu-De
;
Fang, Wai-Chi
;
交大名義發表
In this paper, we propose a system-on-chip(SOC) design of highly effective multi-channel real-time EEG signal processing system based on Online-Recursive Independent Component Analysis (ORICA) algorithm implemented using TSMC's 28nm CMOS technology. In this chip, concepts of system-on-chip (SOC) design and effective system integration technique are well-combined together to realize a highly miniaturized realtime EEG processing system.. The core area and total power consumption of the chip are respectively 1246* 1246 mu m2 and 25.03mW. The chip operations were validated by ADVANTEST V93000 PS1600 and the results obtained match with the software simulation. The average correlation coefficient between original source signals and extracted ORICA signals reaches 0.9572. Eye blink artifact, and facial muscle artifact will be removed automatically. Producing a pure EEG signal is beneficial for realtime data analysis; therefore, this chip design can enhance the reliability and feasibility of EEG-related applications, such as BCI, medical diagnosis and depth of anesthesia detection.
A Customized Convolutional Neural Network Design Using Improved Softmax Layer for Real-time Human Emotion Recognition
(2019-01-01)
Wang, Kai-Yen
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Huang, Yu-De
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Ho, Yun-Lung
;
Fang, Wai-Chi
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電子工程學系及電子研究所
This paper proposes an improved softmax layer algorithm and hardware implementation, which is applicable to an effective convolutional neural network of EEG-based real-time human emotion recognition. Compared with the general softmax layer, this hardware design adds threshold layers to accelerate the training speed and replace the Euler's base value with a dynamic base value to improve the network accuracy. This work also shows a hardware-friendly way to implement batch normalization layer on chip. Using the EEG emotion DEAP[7] database, the maximum and mean classification accuracy were achieved as 96.03% and 83.88% respectively. In this work, the usage of improved softmax layer can save up to 15% of training model convergence time and also increase by 3 to 5% the average accuracy.
A SOC Design of ORICA-based Highly Effective Real-time Multi-channel EEG System
(2019-01-01)
Ho, Yun-Lung
;
Huang, Yu-De
;
Wang, Kai-Yen
;
Fang, Wai-Chi
;
電子工程學系及電子研究所
Independent component analysis (ICA) has been wildly used to improve EEC based application such as brain computer interface (BCI). However, some well know ICA algorithm, such as Infomax ICA, suffering from the problem of convergence latency and make it hard to be apply on real-time application. This paper proposes a highly efficient chip implementation of multi-channel EEC real-time system based on online recursive independent component analysis algorithm (ORICA). The core size of the chip is 1.5525-mm(2) using 28nm CMOS technology. The EEC demonstration board will be implemented with the ORICA chip. The operation frequency and power consumption of the chip are 100 MHz and 17.9 mW respectively. The proposed chip was validated with a real-time circuit integrated system and the average correlation coefficient between simulations results and chip processing results is 0.958.
A SOC Design of ORICA-based Highly Effective Real-time Multi-channel EEG System
(2019-01-01)
Ho, Yun-Lung
;
Huang, Yu-De
;
Wang, Kai-Yen
;
Fang, Wai-Chi
;
電子工程學系及電子研究所
Independent component analysis (ICA) has been wildly used to improve EEC based application such as brain computer interface (BCI). However, some well know ICA algorithm, such as Infomax ICA, suffering from the problem of convergence latency and make it hard to be apply on real-time application. This paper proposes a highly efficient chip implementation of multi-channel EEC real-time system based on online recursive independent component analysis algorithm (ORICA). The core size of the chip is 1.5525-mm(2) using 28nm CMOS technology. The EEC demonstration board will be implemented with the ORICA chip. The operation frequency and power consumption of the chip are 100 MHz and 17.9 mW respectively. The proposed chip was validated with a real-time circuit integrated system and the average correlation coefficient between simulations results and chip processing results is 0.958.
An Edge AI System-on-Chip Design with Customized Convolutional-Neural-Network Architecture for Real-time EEG-Based Affective Computing System
(2019-01-01)
Huang, Yu-De
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Wang, Kai-Yen
;
Ho, Yun-Lung
;
He, Chang-Yuan
;
Fang, Wai-Chi
In this work, we proposed an edge AI CNN chip design for EEG-based affective Computing system by using TSMC 28nm technology. To improve the performance, Artifact Subspace Reconstruction (ASR) and Short-Time Fourier Transform (STFT) were used for our signal pre-processing and features extraction. The time-frequency EEG feature map was obtained with a multi-channel Differential Asymmetry (DASM) method on 6 EEG channels: FP1, FP2, F3, F4, T7, and T8 according to 10-20 system. The total power consumption of the proposed CNN chip was 71.6mW in training mode and 29.5mW in testing mode. We used 32 subjects data from the DEAP database to validate the proposed design, achieving mean accuracies of 83.7%, 84.5%, and 70.51% for Valence-Arousal binary classification and quaternary classification respectively, showing significant performance improvement over the current related works.
Design of Intelligent EEG System for Human Emotion Recognition with Convolutional Neural Network
(2019-01-01)
Wang, Kai-Yen
;
Ho, Yun-Lung
;
Huang, Yu-De
;
Fang, Wai-Chi
;
電子工程學系及電子研究所
Emotions play a significant role in the field of affective computing and Human-Computer Interfaces(HCI). In this paper, we propose an intelligent human emotion detection system based on EEG features with a multi-channel fused processing. We also proposed an advanced convolutional neural network that was implemented in VLSI hardware design. This hardware design can accelerate both the training and classification processes and meet real-time system requirements for fast emotion detection. The performance of this design was validated using DEAP [1] database with datasets from 32 subjects, the mean classification accuracy achieved is 83.88%.
Development and Validation of an EEG-Based Real-Time Emotion Recognition System Using Edge AI Computing Platform With Convolutional Neural Network System-on-Chip Design
(2019-12-01)
Fang, Wai-Chi
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Wang, Kai-Yen
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Fahier, Nicolas
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Ho, Yun-Lung
;
Huang, Yu-De
This study proposed an electroencephalogram (EEG)-based real-time emotion recognition hardware system architecture based on multiphase convolutional neural network (CNN) algorithm implemented on a 28-nm technology chip and on field programmable gate array (FPGA) for binary and quaternary classification. Sample entropy, differential asymmetry, short-time Fourier transform, and a channel reconstruction method were used for emotion feature extraction. In this work, six EEG channels were selected (FP1, FP2, F3, F4, F7, and F8), and EEG images were generated from spectrogram fusions. The complete CNN architecture included training and acceleration for efficient artificial intelligence (AI) edge application, and we proposed a multiphase CNN execution method to accommodate hardware resource constraints. Datasets of 32 subjects from the DEAP database were used to validate the proposed design, exhibiting mean accuracies for valance binary classification and valance-arousal quaternary classification of 83.36% and 76.67%, respectively. The core area and total power consumption of the CNN chip were 1.83 x 1.83 mm(2), respectively, and 76.61 mW. The chip operation was validated using ADVANTEST V93000 PS1600, and the training process and real-time classification processing time took 0.12495 ms and 0.02634 ms for each EEG image, respectively. The proposed EEG-based realtime emotion recognition system included a dry electrode EEG headset, feature extraction processor, CNN chip platform, and graphical user interface, and the execution time costed 450 ms for each emotional state recognition.