Browsing by Author "Huang Po-Tsang"

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Dual-threshold-voltage two-port sub-threshold SRAM cell apparatus
(2011-12-06)
Chang Mu-Tien
;
Huang Po-Tsang
;
Hwang Wei
The invention relates to a dual-threshold-voltage two-port sub-threshold SRAM cell apparatus. The above-mentioned apparatus comprises a first inverter, a second inverter, an access transistor and a read buffer. The first inverter and the second inverter include a plurality of first operating elements and a plurality of second operating elements for storing data. The access transistor is coupled to the first inverter and the second inverter, wherein the first operating elements and the second operating elements are high threshold voltage operating elements and the access transistor is low threshold voltage operating transistor. The read buffer is used for performing a read operation.
Static random access memory with ripple bit lines/search lines for improving current leakage/variation tolerance and density/performance
(2014-07-08)
Chuang Ching-Te
;
Yang Hao-I
;
Lu Chien-Yu
;
Chen Chien-Hen
;
Chang Chi-Shin
A static random access memory includes a pre-charger, a first cell column array/peripheral circuit, and a first ripple buffer. The pre-charger is connected to a first local bit line in order to pre-charge the first local bit line. The first cell column array/peripheral circuit is connected to the first local bit line and has a plurality of cells for temporarily storing data. The cells are connected to the first local bit line. The first ripple buffer is connected to the first local bit line and a second local bit line in order to send the data from the first local bit line to the second local bit line.
SYSTEM AND METHOD FOR ALLOCATING CACHE MEMORY
(2013-01-31)
CHANG Yung
;
Huang Po-Tsang
;
Hwang Wei
Different processor elements in multi-task/multi-core system on chip may have different memory requirements at runtime. The method for adaptively allocating cache memory re-allocates the cache resource by updating the bank assignment table. According to the associativity-based partitioning scheme, centralized memory is separated into several groups of SRAM banks which are numbered differently. These groups are assigned to different processor elements to be L2 caches. The bank assignment information is recoded in bank assignment table, and is updated by system profiling engine. By changing the information in bank assignment table, the cache resource re-allocation for processor elements is achieved.