Browsing by Author "Hudec, Boris"

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3D resistive RAM cell design for high-density storage class memory-a review
(2016-06)
Hudec, Boris
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Hsu, Chung-Wei
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Wang, I-Ting
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Lai, Wei-Li
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Chang, Che-Chia
In this article, we comprehensively review recent progress in the ReRAM cell technology for 3D integration focusing on a material/device level. First we briefly mention pioneering work on high-density crossbar ReRAM arrays which paved the way to 3D integration. We discuss the two main proposed 3D integration schemes-3D horizontally stacked ReRAM vs 3D Vertical ReRAM and their respective advantages and disadvantages. We follow with the detailed memory cell design on important work in both areas, utilizing either filamentary or interface-limited switching mechanisms. We also discuss our own contributions on HfO2-based filamentary 3D Vertical ReRAM as well as TaOx/TiO2 bilayer-based self-rectifying 3D Vertical ReRAM. Finally, we summarize the present status and provide an outlook for the nearterm future.
Challenges and Opportunities toward Online Training Acceleration using RRAM-based Hardware Neural Network
(2017-01-01)
Chang, Chih-Cheng
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Liu, Jen-Chieh
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Shen, Yu-Lin
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Chou, Teyuh
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Chen, Pin-Chun
This paper highlights the feasible routes of using resistive memory (RRAM) for accelerating online training of deep neural networks (DNNs). A high degree of asymmetric nonlinearity in analog RRAMs could be tolerated when weight update algorithms are optimized with reduced training noise. Hybrid-weight Net (HW-Net), a modified multilayer perceptron (MLP) algorithm that utilizes hybrid internal analog and external binary weights is also proposed. Highly accurate online training could be realized using simple binary RRAMs that have already been widely developed as digital memory.
Crossbar array of selector-less TaOx/TiO2 bilayer RRAM
(2015-11-01)
Chou, Chun-Tse
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Hudec, Boris
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Hsu, Chung-Wei
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Lai, Wei-Li
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Chang, Chih-Cheng
In this work, we have implemented self-rectifying TaOx/TiO2 REAM in a selector-less 6 x 6 crossbar array with various desiring features, including: (1) simple fabrication using only three masks, (2) high self-rectifying ratio up to 10(3) for sneak current suppression, (3) stable bipolar resistive-switching characteristics without the need for electro-forming and current compliance, (4) data retention time over 10(4) s, and (5) robust READ and WRITE disturb immunity. Finally, an achievable array size of 1 Mb was simulated using an All-LPU read scheme and a V/3 write scheme. (C) 2015 Elsevier Ltd. All rights reserved.
Interchangeable Hebbian and Anti-Hebbian STDP Applied to Supervised Learning in Spiking Neural Network
(2018-01-01)
Chang, Che-Chia
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Chen, Pin-Chun
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Hudec, Boris
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Liu, Po-Tsun
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Hou, Tuo-Hung
This work provides a complete framework, including device, architecture, and algorithm, for implementing bio-inspired supervised spiking neural networks (SNNs) on hardware. An analog synapse with atypical dual bipolar resistive-switching (D-BRS) modes demonstrates interchangeable Hebbian spiking-timing-dependent plasticity (STDP) and anti-Hebbian STDP, and it is capable of implementing supervised ReSuMe SNNs in crossbar arrays. By using an "exchange" update scheme, accurate supervised learning (similar to 96% for MNIST) is achieved in a compact network.
Interface engineered HfO2-based 3D vertical ReRAM
(2016-06-02)
Hudec, Boris
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Wang, I-Ting
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Lai, Wei-Li
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Chang, Che-Chia
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Jancovic, Peter
We demonstrate a double-layer 3D vertical resistive random access memory (ReRAM) stack implementing a Pt/HfO2/TiN memory cell. The HfO2 switching layer is grown by atomic layer deposition on the sidewall of a SiO2/TiN/SiO2/TiN/SiO2 multilayer pillar. A steep vertical profile was achieved using CMOS-compatible TiN dry etching. We employ in situ TiN bottom interface engineering by ozone, which results in (a) significant forming voltage reduction which allows for forming-free operation in AC pulsed mode, and (b) non-linearity tuning of low resistance state by current compliance during Set operation. The vertical ReRAM shows excellent read and write disturb immunity between vertically stacked cells, retention over 10(4) s and excellent switching stability at 400 K. Endurance of 10(7) write cycles was achieved using 100 ns wide AC pulses while fast switching speed using pulses of only 10 ns width is also demonstrated. The active switching region was evaluated to be located closer to the bottom interface which allows for the observed high endurance.
Internal current amplification induced by dielectric hole trapping in monolayer MoS2 transistor
(2017-11-24)
Liu, Pang-Shiuan
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Lin, Ching-Ting
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Hudec, Boris
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Hou, Tuo-Hung
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電子工程學系及電子研究所
Carrier transport in layered transition-metal dichalcogenides is highly sensitive to surrounding charges because of the atomically thin thickness. By exploiting this property, we report a new internal current amplification mechanism through positive feedback induced by dielectric hole trapping in a MoS2 back-gate transistor on a tantalum oxide substrate. The device exhibits an extremely steep subthreshold slope of 17 mV/decade, which is strongly dependent on the substrate material and drain bias. The steep subthreshold slope is attributed to the internal current amplification arising from the positive feedback between hole generation in MoS2 triggered by large lateral electric field and Schottky barrier narrowing induced by localized hole trapping in tantalum oxide near the source contact.
Memristive devices by ALD: design aspects for high density 3D arrays for memory and neuromorphic applications
(2018-01-01)
Hudec, Boris
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Chang, Che-Chia
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Hou, Tuo-Hung
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive Synapse
(2018-03-01)
Chang, Chih-Cheng
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Chen, Pin-Chun
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Chou, Teyuh
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Wang, I-Ting
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Hudec, Boris
Asymmetric nonlinear weight update is considered as one of the major obstacles for realizing hardware neural networks based on analog resistive synapses, because it significantly compromises the online training capability. This paper provides new solutions to this critical issue through co-optimization with the hardware-applicable deep-learning algorithms. New insights on engineering activation functions and a threshold weight update scheme effectively suppress the undesirable training noise induced by inaccurate weight update. We successfully trained a two-layer perceptron network online and improved the classification accuracy of MNIST handwritten digit data set to 87.8%/94.8% by using 6-/8-b analog synapses, respectively, with extremely high asymmetric nonlinearity.
Recommended Methods to Study Resistive Switching Devices
(2019-01-01)
Lanza, Mario
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Wong, H-S Philip
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Pop, Eric
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Ielmini, Daniele
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Strukov, Dimitri
Resistive switching (RS) is an interesting property shown by some materials systems that, especially during the last decade, has gained a lot of interest for the fabrication of electronic devices, with electronic nonvolatile memories being those that have received the most attention. The presence and quality of the RS phenomenon in a materials system can be studied using different prototype cells, performing different experiments, displaying different figures of merit, and developing different computational analyses. Therefore, the real usefulness and impact of the findings presented in each study for the RS technology will be also different. This manuscript describes the most recommendable methodologies for the fabrication, characterization, and simulation of RS devices, as well as the proper methods to display the data obtained. The idea is to help the scientific community to evaluate the real usefulness and impact of an RS study for the development of RS technology.
Resistive random access memory (RRAM) technology: From material, device, selector, 3D integration to bottom-up fabrication
(2017-12-01)
Chen, Hong-Yu
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Brivio, Stefano
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Chang, Che-Chia
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Frascaroli, Jacopo
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Hou, Tuo-Hung
Emerging non-volatile memory technologies are promising due to their anticipated capacity benefits, non-volatility, and zero idle energy. One of the most promising candidates is resistive random access memory (RRAM) based on resistive switching (RS). This paper reviews the development of RS device technology including the fundamental physics, material engineering, three-dimension (3D) integration, and bottom-up fabrication. The device operation, physical mechanisms for resistive switching, reliability metrics, and memory cell selector candidates are summarized from the recent advancement in both industry and academia. Options for 3D memory array architectures are presented for the mass storage application. Finally, the potential application of bottom-up fabrication approaches for effective manufacturing is introduced.
Semi-Empirical RC Circuit Model for Non-Filamentary Bi-Layer OxRAM Devices
(2020-03-01)
Majumdar, Swatilekha
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Chen, Ying
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Hudec, Boris
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Hou, Tuo-Hung
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Suri, Manan
In this brief, we present a semi-empirical RC-circuit-based compact model for non-filamentary bi-layer oxide-based random access memory (OxRAM) devices. The proposed RC model captures both dc and pulse behaviors of the OxRAM devices. Additionally, the model is also able to reproduce the electrical behavior of these devices on application of arbitrary SET/RESET pulses. The model is verified for three non-filamentary OxRAM devices: Ta/HfO2/Al:TiO2/TiN, TiN/TaO/HfOx/TiON/TiN, and Al/AlO sigma /Ta2O5-x/TaOy/W. Through this model, simulation versus experimental error of less than 10% is achieved.
SLIM: Simultaneous Logic-in-Memory Computing Exploiting Bilayer Analog OxRAM Devices
(2020-02-13)
Kingra, Sandeep Kaur
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Parmar, Vivek
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Chang, Che-Chia
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Hudec, Boris
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Hou, Tuo-Hung
von Neumann architecture based computers isolate computation and storage (i.e. data is shuttled between computation blocks (processor) and memory blocks). The to-and-fro movement of data leads to a fundamental limitation of modern computers, known as the Memory wall. Logic in-Memory (LIM)/In-Memory Computing (IMC) approaches aim to address this bottleneck by directly computing inside memory units thereby eliminating energy-intensive and time-consuming data movement. Several recent works in literature, propose realization of logic function(s) directly using arrays of emerging resistive memory devices (example- memristors, RRAM/ReRAM, PCM, CBRAM, OxRAM, STT-MRAM etc.), rather than using conventional transistors for computing. The logic/embedded-side of digital systems (like processors, micro-controllers) can greatly benefit from such LIM realizations. However, the pure storage-side of digital systems (example SSDs, enterprise storage etc.) will not benefit much from such LIM approaches as when memory arrays are used for logic they lose their core functionality of storage. Thus, there is the need for an approach complementary to existing LIM techniques, that's more beneficial for the storage-side of digital systems; one that gives compute capability to memory arrays not at the cost of their existing stored states. Fundamentally, this would require memory nanodevice arrays that are capable of storing and computing simultaneously. In this paper, we propose a novel 'Simultaneous Logic in-Memory' (SLIM) methodology which is complementary to existing LIM approaches in literature. Through extensive experiments we demonstrate novel SLIM bitcells (1T-1R/2T-1R) comprising non-filamentary bilayer analog OxRAM devices with NMOS transistors. Proposed bitcells are capable of implementing both Memory and Logic operations simultaneously. Detailed programming scheme, array level implementation, and controller architecture are also proposed. Furthermore, to study the impact of proposed SLIM approach for real-world implementations, we performed analysis for two applications: (i) Sobel Edge Detection, and (ii) Binary Neural Network- Multi layer Perceptron (BNN-MLP). By performing all computations in SLIM bitcell array, huge Energy Delay Product (EDP) savings of approximate to 75x for 1T-1R (approximate to 40x for 2T-1R) SLIM bitcell were observed for edge-detection application while EDP savings of approximate to 3.5x for 1T-1R (approximate to 1.6x for 2T-1R) SLIM bitcell were observed for BNN-MLP application respectively, in comparison to conventional computing. EDP savings owing to reduction in data transfer between CPU <-> memory is observed to be approximate to 780x (for both SLIM bitcells).
Three dimensional integration of ReRAMs
(2018-01-01)
Hudec, Boris
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Chang, Che-Chia
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Wang, I-Ting
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Frohlich, Karol
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Hou, Tuo-Hung
Storage-class memory, non-volatile, ultra-dense and lightning fast, may enable memory-driven computing to revolutionize the current architectures leading to an on-chip processing of vast amount of data. 3D vertical resistive random access memory (ReRAM) is a hot candidate for storage-class memory. In this talk we review current state-of-the-art works which offer promising solutions, utilizing either filamentary or non-filamentary ReRAM designs, including our own. We will discuss the pros and cons of different approaches and summarize the open problems, drawing possible solutions.