Browsing by Author "Hung, C. M."

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A Circuit Level Variability Prediction of Basic Logic Gates in Advanced Trigate CMOS Technology
(2014)
Hsieh, E. R.
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Hung, C. M.
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Wang, T. Y.
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Chung, Steve S.
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Huang, R. M.
Variability has been one of the major scaling issues in advancing the CMOS technology. In this paper, a variation model from the device level to circuit level has been proposed and demonstrated on advanced trigate FinFETs. First, a simple and accurate transport model was developed to model variability at the device level. It was then implemented in Spice and the calculation of variation of basic logic gate building block was demonstrated with only W/L and the slopes, A(vt), A(gm), in the Pelgrom plot, as inputs. Finally, a unified simple analytic form was developed to predict the variability of various basic logic circuits regardless of the number of devices and the complexity of circuits.
A Comprehensive Transport Model for High Performance HEMTs Considering the Parasitic Resistance and Capacitance Effects
(2014)
Hung, C. M.
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Li, K. C.
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Hsieh, E. R.
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Wang, C. T.
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Kou, C. I.
HEMT suffers from parasitic resistance (R-sd) and capacitance(C-gd) effects with the shrinking of channel length, leading to degraded performance in logic and RF applications. A new while simple method to extract parasitic RC has been proposed to construct accurate transport parameters in HEMTs. In comparison to the constant-R-sd method, this new voltage dependent method provides more convincing results, especially for very short channel devices. On the other hand, an accurate C-gd correction method has also been incorporated to adequately represent the mobility. Finally, a guideline to design high performance HEMTs has been proposed.