Browsing by Author "Hung, Chia-Tse"

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A 40 Gb/s PAM-4 Receiver with 2-Tap DFE Based on Automatically Non-Even Level Tracking
(2018-01-01)
Hung, Chia-Tse
;
Huang, Yu-Ping
;
Chen, Wei-Zen
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 40 Gbh PAM-4 receiver comprised of continuous-time linear equalizer (CTLE) and 2-tap decision-feedback equalizers (DFE) based on a novel level tracking circuit (ANLT) is proposed. A sign-sign LMS engine is embedded for the DFE and ANLT coefficients adaptation to accommodate different channel loss. The ANLT is capable of automatically tracking a non-evenly spaced PAM-4 signal, allowing the receiver to demodulate a distorted input with 2-bit flash ADCs. Fabricated in a TSMC 40nm CMOS technology, the whole receiver consumes 241.8 m1V at 40 Gb/s operation. Core area is 0.274mm(2).