Browsing by Author "Hung, Chung-Chih"

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1-V linear CMOS transconductor with-65 dB THD in nano-scale CMOS technology
(2007)
Lo, Tien-Yu
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Hung, Chung-Chih
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電信工程研究所
;
Institute of Communications Engineering
This paper presents a high linearity MOSFET-only transconductor based on differential structures. The linearity is improved by mobility compensation techniques as the device size is scaled down in the nano-scale CMOS technology. Transconductance tuning could be achieved by transistors operating in the linear region. The simulated total harmonic distortion (THD) under 1-V power supply voltage shows 12 dB improvement of the proposed version, and -65 dB TTID can be achieved for a 1 MHz 700 mV(pp) differential input. Monte-Carlo simulation over the corner variation and transistor mismatch guarantees the shown performance. The static power consumption is 130 mu W. Simulation results demonstrate the agreement with theoretical analyses.
10-Bit SAR ADC With Novel Pseudo-Random Capacitor Switching Scheme
(2019-01-01)
Hsu, Pai-Hsiang
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Lee, Yueh-Ru
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Hung, Chung-Chih
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電機工程學系
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Department of Electrical and Computer Engineering
This paper presents a pseudo-random capacitor switching scheme. Taking 1% of capacitor mismatch into account, after applying the pseudo-random switching scheme to the SAR ADC matlab behavioral model, for 500 Monte Carlo simulations, the missing code (Minimum DNL=-1) occurrence is reduced from 176 to 3, and the other performance indicators are also improved significantly. The circuit was fabricated by using 0.18-mu m 1P6M TSMC CMOS process. With a sampling rate of 1KS/s and 50Hz input frequency, the measured SNDR and SFDR achieves 57.11dB and 75.37dB respectively while consuming a power of 7.68 mu W. With a sampling rate of 48KS/s and 500Hz input frequency, the measured SNDR and SFDR achieves 56.91dB and 74.47dB respectively while consuming a power of 7.93 mu W. With a sampling rate of IMS/s and 50KHz input frequency, the measured SNDR and SFDR achieves 58.71dB and 77.89dB respectively while consuming a power of 102 mu W. The measured INL is 0.54/-0.78 LSB, and DNL is 0.67/-0.82 LSB. The circuit is applicable for various bio-medical applications.
15MHZ WIDE TUNING-RANGE OTA WITH-69dB HD3 AND ITS APPLICATION TO GM-C FILTER
(2011)
Lin, Jun-Ye
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Chang, Wei-Hsiu
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Hung, Chung-Chih
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電機工程學系
;
Department of Electrical and Computer Engineering
This paper presents a high linearity operational transconductance amplifier (OTA). The OTA circuit combines the techniques of the double differential pairs (DDP) and Source-degenerated current mirrors to achieve high linearity in a large GM tuning range. With the Gm values ranged from 60 mu S to 130 mu S, the HD3 of the OTA is below -69dB at 15MHz. The OTA has been applied to a fourth-order linear phase low-pass filter for high speed system. The fourth-order low-pass filter with the cutoff frequency of 15MHz has been implemented. The filter is designed by 0.18-mu m CMOS process technology, the HD3 performance is about -53dB, and the group delay variation is below 5% at cutoff frequency.
1V 4.8mW 42.6-45.6GHz CMOS Voltage Controlled Oscillator for IEEE 802.15.3c Wireless Communication System
(2010-01-01)
Huang, Zhe-Yang
;
Hung, Chung-Chih
;
電信工程研究所
;
Institute of Communications Engineering
A 1V 4.8mW 42.6GHz-45.6GHz CMOS Voltage Controlled Oscillator (VCO) is designed for IEEE 802.15.3c mm-wave wireless communication system. The oscillator provides a center frequency of 44.1GHz and is implemented in 90nm Logic CMOS technology. The oscillator core consumes 4.8mW through 1.0V supply voltage and the active area is 0.05mm(2) only. A tuning range of 3.0GHz (42.6GHz-45.6GHz) with maximum control voltage of 1.0V can be achieved. And the phase noise is -93.7 dBc/Hz at 1MHz offset from the center frequency. The calculated figure-of-merit (FOM) is -180.1 dB.
-65dB HD3 CMOS TUNABLE OTA WITH MOBILITY REDUCTION COMPENSATION
(2011)
Cheng, Shih-Tung
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Chang, Wei-Hsiu
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Hung, Chung-Chih
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電機工程學系
;
Department of Electrical and Computer Engineering
This paper presents a high linearity operational transconductance amplifier (OTA) base on the technique of mobility reduction compensation, which achieves great linearity improvement and has wide input range at low power consumption. The third-order harmonic distortion (HD3) of the OTA is about -65dB at 1MHz for a 1.2-V-pp differential input. The OTA was designed by the TSMC 0.18-mu m CMOS process technology. For 1.8-V supply voltage, the static power consumption is only 0.427mW.
A 0.35-V 240-W Fast-Lock and Low-Phase-Noise Frequency Synthesizer for Implantable Biomedical Applications
(2019-12-01)
Wang, Shih-Hsing
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Hung, Chung-Chih
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電機資訊學士班
;
Undergraduate Honors Program of Electrical Engineering and Computer Science
For implantable frequency synthesizers, realizing ultra-low voltage (ULV) and low power in addition to meeting PLL targets, fast lock and low phase noise, poses a difficult challenge. This paper presents techniques to achieve PLL targets as well as ULV and low power in the same chip through the use of a regular CMOS technology node. A curvature-PFD technique achieves both faster locking and lower jitter compared with conventional techniques. A two-step switching technique substantially reduces the power consumption in current mirrors and reduce noise when switching from a charge pump. Leakage analysis and subthreshold-leakage-reduction technique reduce reference spur and jitter to the voltage-controlled oscillator (VCO). A dither technique randomizes and averages reference spurs. The proposed chip was implemented in 90-nm CMOS technology; the 0.35-V medical-band frequency synthesizer consumes 238-W power while generating output clock of 401.8 to 431.31-MHz and exhibiting a phase noise of -105.7 dBc/Hz at 1-MHz frequency offset with 20 s locking time.
A 0.3V 10b 3MS/s SAR ADC With Comparator Calibration and Kickback Noise Reduction for Biomedical Applications
(2020-06-01)
Wang, Shih-Hsing
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Hung, Chung-Chih
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電機資訊學士班
;
Undergraduate Honors Program of Electrical Engineering and Computer Science
This paper presents a 10-bit successive approximation analog-to-digital converter (ADC) that operates at an ultralow voltage of 0.3 V and can be applied to biomedical implants. The study proposes several techniques to improve the ADC performance. A pipeline comparator was utilized to maintain the advantages of dynamic comparators and reduce the kickback noise. Weight biasing calibration was used to correct the offset voltage without degrading the operating speed of the comparator. The incorporation of a unity-gain buffer improved the bootstrap switch leakage problem during the hold period and reduced the effect of parasitic capacitances on the digital-to-analog converter. The chip was fabricated using 90-nm CMOS technology. The data measured at a supply voltage of 0.3 V and sampling rate of 3 MSps for differential nonlinearity and integral nonlinearity were +0.83/-0.54 and +0.84/-0.89, respectively, and the signal-to-noise plus distortion ratio and effective number of bits were 56.42 dB and 9.08 b, respectively. The measured total power consumption was 6.6 mu W at a figure of merit of 4.065 fJ/conv.-step.
A 1 GHz Equiripple Low-Pass Filter With a High-Speed Automatic Tuning Scheme
(2011-02-01)
Lo, Tien-Yu
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Hung, Chung-Chih
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電機工程學系
;
Department of Electrical and Computer Engineering
A continuous-time fourth-order equiripple linear phase G(m) - C filter with an automatic tuning circuit is presented. A high speed OTA based on the inverter structure is realized. The combined common-mode feedforward and common-mode feedback circuit ensures the input and output common-mode stability. The gain performance could be maintained by combining an equivalent negative resistor circuit at the output nodes. Transconductance tuning can be achieved by adjusting the bulk voltage by using the deep-NWELL technology. The modified automatic tuning circuit relaxes the speed requirement of the tuning blocks. Through the use of the operational transconductance amplifier as a building block with the automatic tuning scheme, the filter -3 dB cutoff frequency is 1 GHz with the group delay less than 4% variation up to 1.5 fc frequency. The -43 dB of IM3 at filter cutoff frequency is obtained with -4 dbm two-tone signals. Implemented in 0.18-mu m CMOS process, the chip occupies 1 mm(2) and consumes 175 mW at a 1.5-V supply voltage.
A 1 GHz OTA-Based low-pass filter with a high-speed automatic tuning scheme
(2007)
Lo, Tien-Yu
;
Hung, Chung-Chih
;
電信工程研究所
;
Institute of Communications Engineering
A continuous-time 4th-order equiripple linear phase G.-C filter with an automatic tuning circuit is presented. A high speed OTA based on the inverter structure is realized. The combined CMFF and CMFB circuit ensures the input and output common-mode stability. The gain performance could be maintained by combining a negative resistor at the output nodes. Transconductance tuning can be achieved by adjusting the bulk voltage by using the Deep-NWELL technology. Through the use of the OTA as a building block with a modified automatic tuning scheme, the filter -3dB cutoff frequency is 1GHz with the group delay less than 4% variation up to 1.5fc frequency. The -43dB of IM3 at filter cutoff frequency is obtained with -4dbm two tone signals. Implemented in 0.18-mu m CMOS process, the chip occupies 1mm(2) and consumes 175mW at a 1.5-V supply voltage.
A 1-V 50-MHz pseudodifferential OTA with compensation of the mobility reduction
(2007-12-01)
Lo, Tien-Yu
;
Hung, Chung-Chih
;
電信工程研究所
;
Institute of Communications Engineering
This brief presents a high-linearity operational transconductance amplifier (OTA) based on pseudodifferential structures. The linearity is improved by mobility compensation techniques as the device size is scaled down to achieve high speed operation. Transconductance tuning could be achieved by a MOS operating in the linear region. The OTA fabricated in the 0.18-mu m CMOS process occupies a small area of 4.5 X 10(-3) mm(2). The measured third-order intermodulation (IM3) distortion with a 400 mV(pp) differential input under 1-V power supply voltage remains below -52 dB for frequency up to 50 MHz. The static power consumption is 2.5 mW. Experimental results demonstrate the agreement with theoretical analyses.
A 1-V G(m)-C Low-Pass Filter for UWB Wireless Application
(2008)
Lo, Tien-Yu
;
Hung, Chung-Chih
;
電信工程研究所
;
Institute of Communications Engineering
This paper proposes a high performance G.-C equiripple linear phase low-pass filter for UWB wireless application. The proposed OTA is designed under low power supply voltage consideration while its gain, excess phase, and linearity are well maintained. The common-mode control system, including common-mode feedback (CMFB) and common-mode feedforward (CMFF) circuits, is added to ensure stability of the proposed filter. Measurement results show that the inter-modulation distortion (IM3) of -40dB can be achieved with 250MHz 400mV(pp) balanced differential input signals. The filter works in 1-V supply voltage and its power consumption is 32mW.
A 1v CMOS low-noise amplifier with inductive resonated for 3.1-10.6GHz UWB wireless receiver
(2007)
Huang, Zhe-Yang
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Huang, Che-Cheng
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Chen, Chun-Chieh
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Hung, Chung-Chih
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電信工程研究所
In this paper a low power and low-noise amplifier (LNA) is designed for ultra-wideband (UWB) system. The design consists of a wideband input impedance matching network, two stages common-source amplifier with inductive resonated load and an output buffer measurement purpose; it is fabricated in TSMC 0.18um standard RF CMOS process. The measured UWB LNA gives 12.0dB gain and 8.0GHz 3dB bandwidth (3.0-11.0GHz) while consuming only 7.3mW through a 1.0V supply including the buffer. Over the 3.1-10.6 GHz frequency band, a minimum noise figure of 4.2dB and input return loss lower than -8.7dB have been achieved.
A 1V-2.39MW capacitor-coupling resonated low noise amplifier for 3-5GHz ultra-wideband system
(2007)
Huang, Zhe-Yang
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Huang, Che-Cheng
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Chen, Chun-Chieh
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Hung, Chung-Chih
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電信工程研究所
In this paper a high gain, low power, low-noise amplifier (LNA) is designed for ultra-wideband (UWB) system. The design consists of a wideband input impedance matching network, one stage cascodc amplifier with capacitor-coupling resonated load and it is fabricated in UMC 0.18um standard RF CMOS process. The LNA gives 10.3dB gain and 1.8GHz 3dB bandwidth (3.1 - 4.9GHz) while consuming only 2.39mW through a 1.0V supply. Over the 3.1 - 4.9GHz frequency band, a minimum noise figure of 4.5dB and input return loss lower than -5.7dB have been achieved.
A 250 MHz low voltage low-pass G(m)-C filter
(2012-06-01)
Lo, Tien-Yu
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Hung, Chung-Chih
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電機工程學系
;
Department of Electrical and Computer Engineering
A high speed and high linearity G(m)-C low-pass filter is presented. The proposed OTA is designed under low power supply voltage consideration while its gain, excess phase, and linearity are well maintained. The common-mode control system, including common-mode feedback and common-mode feedforward circuits, is added to ensure stability of the proposed filter. Measurement results show that the inter-modulation distortion of -40 dB can be achieved with 250 MHz 400 mV(pp) differential input signals. The filter works in 1 - V supply voltage and its power consumption is 32 mW.
A 40-MHz double differential-pair CMOS OTA with-60-dB IM3
(2008-02-01)
Lo, Tien-Yu
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Hung, Chung-Chih
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電信工程研究所
;
Institute of Communications Engineering
A configuration of a linearized operational transconductance amplifier (OTA) for low-voltage and high-frequency applications is proposed. By using double pseudodifferential pairs and the source-degeneration structure under nano-scale CMOS technology, the norlinearity caused by short channel effect from a small feature size can be minimized. A robust common-mode control system is designed for input and output common-mode stability and thus reduces distortion caused by common-mode voltage variation. Mining ability can be achieved by using MOS transistors in the linear region. The linearity of the OTA is about -60-dB third-order inter-modulation (IM3) distortion for up to 0.9 V-pp at 40 MHz. This OTA was fabricated by the TSMC 180-nm deep n-well CMOS process. It occupies a small area of 15.1 X 10(-3) mm(2) and the power consumption is 9.5 mW under a 1.5-V supply voltage.
A 5.8 mW Continuous-Time Delta Sigma Modulator With 20 MHz Bandwidth Using Time-Domain Flash Quantizer
(2015-12-01)
Chen, Zong-Yi
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Hung, Chung-Chih
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電機資訊學士班
;
Undergraduate Honors Program of Electrical Engineering and Computer Science
This paper presents a power-efficient realization of a third-order continuous-time delta-sigma (CT - Delta Sigma) modulator with 3-bit time-domain flash quantizer (TDFQ) and data-weighted averaging (DWA) based on the shifter output and input. Using the time-domain quantizer can overcome design issues in low voltage supply during CMOS downscaling. The CT - Delta Sigma modulator uses the TDFQ instead of a voltage-domain quantizer to reduce power consumption. The proposed TDFQ solves the linearity problem of the delay-based voltage-to-time converter (VTC) without calibration circuit while also increasing the quantizer input range and saving energy. Moreover, in order to reduce the mismatch effects of a multibit DAC and achieve low power consumption, implementation of a low-power DWA circuit is proposed without using a digital adder to calculate pointer for controlling barrel shift circuit. This chip was fabricated in CMOS 90 nm process. The proposed CT - Delta Sigma modulator consumes 5.8 mW from 1.0 V and achieves peak SNDR of 65.3 dB over the 20 MHz bandwidth, which results in FOM_W = 96.3 fJ/level and FOM_S = 161 dB.
A 65-77 GHz low power, meander-type transmission line CMOS low-noise amplifier
(2015-07-10)
Huang, Zhe-Yang
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Chen, Chun-Chieh
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Hung, Chung-Chih
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電機資訊學士班
;
Undergraduate Honors Program of Electrical Engineering and Computer Science
A 65-77 GHz low power, meander-type transmission line CMOS low-noise amplifier for E-band millimetre-wave communication using 90 nm MS/RF CMOS process is demonstrated. The low-noise amplifier consists of multi-stage cascaded common-source amplifiers with optimized noise figure, power gain, and power consumption. The LNA achieves 11.7 dB power gain, 5.5 dB noise figure, and 17.7 mW power consumption. The meander-type transmission line circuit design is adopted to reduce chip area; the total transmission line area in LNA is only 0.024 mm(2).
A Bone-Guided Cochlear Implant CMOS Microsystem Preserving Acoustic Hearing
(2017-01-01)
Qian, Xin-Hong
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Wu, Yi-Chung
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Yang, Tzu-Yi
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Cheng, Cheng-Hsiang
;
Chu, Hsing-Chien
In this paper, a bone-guided cochlear implant (BGCI) SOC microsystem is proposed and designed. The BGCI microsystem uses four or more electrodes placed on the bone surface of the cochlea and one on the round window to preserve partially the acoustic hearing. The external SOC of the BGCI processes the acoustic signals and generates stimulation patterns and command that are transmitted to the implanted chip through the 13.56MHz wireless power and bidirectional data telemetry. The implanted chip with 4-channel high-voltage-tolerant stimulator generates biphasic stimulation currents up to 800 mu A and sends back the power indication and electrode impedance error signals to the external SOC. Electrical tests on the fabricated BGCI has been performed. The in-vivo animal tests on guinea pigs has shown the evoked Wave III of EABR waveforms. The proposed BGCI can be applied to patients with high-frequency hearing loss, tinnitus, and dizziness.
A Capacitor-Free CMOS Low-Dropout Voltage Regulator
(2009)
Chen, Chia-Min
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Hung, Chung-Chih
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電信工程研究所
;
Institute of Communications Engineering
This paper presents novel frequency compensation techniques for low-dropout (LDO) voltage regulator. An enhanced active feedback frequency compensation is employed to improve its frequency response. This LDO can provide high stability for loading current range up to 100 mA without loading capacitors. Moreover, the total compensation capacitors only require 7 pF for this technique. This allows us to integrate the compensation capacitors within the LDO chip easily. The proposed LDO regulator was designed using TSMC 0.35-mu m CMOS technology. With an active area of 0.14 mm(2), the quiescent current is only 40 mu A. The input voltage is ranged from 1.73 V to 5 V for loading current of 100 mA and the output voltage of 1.5 V. The main advantage of this approach is that the LDO circuit can be stable when we connect external load capacitors with ultra low ESR, or even when we eliminate the load capacitors.
A CMOS low-noise amplifier with impedance feedback for ultra-wideband wireless receiver system
(2008)
Huang, Zhe-Yang
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Huang, Che-Cheng
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Chen, Chun-Chieh
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Hung, Chung-Chih
;
Jou, Christina F.
In this paper, a CMOS low-noise amplifier (LNA) is designed for ultra-wideband (UWB) wireless receiver system. The design consists of a wideband input impedance matching network, a cascoded amplifier with shunt-peaked load, a RLC-impedance feedback loop and an output buffer for measurement purpose. It is fabricated in TSMC 0.18um standard RF CMOS process. The LNA gives 11.5dB maximum power gain between 3.1GHz-5.0GHz while consuming 5.7mW through a 1.8V supply voltage. Over the 3.1GHz-5.0GHz frequency band, the minimum noise figure (NF) is 4.7dB. Input return loss lower than -12.7 dB in all bandwidth have been achieved.