Browsing by Author "Hung, Jui-Hui"

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A 1.45Gb/s (576,288) LDPC decoder for 802.16e standard
(2007)
Hung, Jui-Hui
;
Chen, Sau-Gee
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this work, a (576,288) LDPC decoder for 802.16e standard is presented. This design is a partially parallel architecture based on a new optimally reordered decoding scheme. Besides, the proposed architecture handles two different code words at a time to achieve 100% utilization rate of both CNU and BNU. As a result, high throughput and low hardware complexity are achieved. In chip implementation, the proposed design achieves a data rate of 1.45Gb/s with 10 iterations and 7 quantization bits, at the cost of 881K gates, based on UMC 0.18 mu m process technology.
A Fast Systematic Optimized Comparison Algorithm for CNU Design of LDPC Decoders
(2011-11-01)
Hung, Jui-Hui
;
Chen, Sau-Gee
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work first investigates two existing check node unit (CNU) architectures for LDPC decoding: self-message-excluded CNU (SME-CNU) and two-minimum CNU (TM-CNU) architectures, and analyzes their area and timing complexities based on various realization approaches. Compared to TM-CNU architecture, SME-CNU architecture is faster in speed but with much higher complexity for comparison operations. To overcome this problem, this work proposes a novel systematic optimization algorithm for comparison operations required by SME-CNU architectures. The algorithm can automatically synthesize an optimized fast comparison operation that guarantees a shortest comparison delay time and a minimized total number of 2-input comparators. High speed is achieved by adopting parallel divide-and-conquer comparison operations, while the required comparators are minimized by developing a novel set construction algorithm that maximizes shareable comparison operations. As a result, the proposed design significantly reduces the required number of comparison operations, compared to conventional SME-CNU architectures, under the condition that both designs have the same speed performance. Besides, our preliminary hardware simulations show that the proposed design has comparable hardware complexity to low-complexity TM-CNU architectures.
A High-Performance Multibit-Flipping Algorithm for LDPC Decoding
(2009)
Hung, Jui-Hui
;
Chen, Sau-Gee
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
For LDPC decoding, bit-flipping (BF) algorithms are much simpler than the min-sum algorithms (MSA). However, BF algorithms have the disadvantages of poorer performances and higher iteration counts than MSA. This paper introduces the concepts of low correlation search and culprit vote to further improve the efficiency of the existing BF algorithms. High decoding performances and low iteration number are achieved by flipping those bits with low correlation as much as possible and introducing an additional syndrome vote procedure. As a result, the proposed algorithm can achieve significant decoding performance which is very close to the min-sum algorithm (MSA) but with much lower computation complexity.
A Low-Complexity High-Performance Decoding Algorithm for Fixed-Point LDPC Decoders
(2008)
Hung, Jui-Hui
;
Chen, Sau-Gee
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The bit-error-rate (BER) performance of an LDPC decoding algorithm will be seriously degraded when the algorithm is realized with fixed-point implementation in practical applications, due to the introduced quantization errors and rounding errors. To remedy the problem, this paper proposes an improved min-sum algorithm (MSA), called CMVP algorithm. It achieves better performances than the popular min-sum algorithm (MSA), under the condition of the same fixed-point precision. Besides, the hardware overhead of the new algorithm over conventional MSA is small. On the other hand, under the condition of comparable performances, MSA algorithm needs a higher fixed-point precision and hardware costs than the new CMVP algorithm, according to the simulations and hardware synthesis results. The new algorithm also works well in a wide range of code rates and code lengths.
A New Genetics-Aided Message Passing Decoding Algorithm for LDPC Codes
(2012-01-01)
Hung, Jui-Hui
;
Lu, Yi-De
;
Chen, Sau-Gee
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The popular LDPC decoding algorithms based on the message passing (MP) algorithm have high decoding performances. However, they are noticeably inferior to the maximum likelihood (ML) decoding algorithm. This work proposes a genetics-aided message passing (GA-MP) algorithm by applying a new genetic algorithm to MP algorithm. As a result, significantly performance improvement over MP algorithm can be achieved. Besides, compared with other genetic-aided decoding algorithms, the proposed algorithm has much better performances and much lower computational complexity. Simulations show that the decoding performance of GA-MP algorithm can achieve performances very close to the algorithm, while outperform MP algorithm. Besides, its performance will grow proportionally with the generation number without leveling off as observed in conventional MP algorithms, under high SNR condition.
A Real-Time High-Throughput LDPC Decoder for IEEE 802.3an Standard
(2010)
Hung, Jui-Hui
;
Kao, Li-Wei
;
Chen, Sau-Gee
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The existing LDPC decoders are mostly based on the belief-propagation (BP) algorithms, due to good BER performances. However, they demand large chip areas. This paper proposes a high-throughput LDPC decoder based on the bit-flipping algorithms, for the (2048, 1723) RS-LDPC code adopted in the IEEE 802.3an standard. High decoding performances and low iteration numbers are achieved by introducing a strategy of flipping low-correlation bits and an additional syndrome vote scheme. As a result, the decoding performance is very close to the most popular BP-based min-sum algorithm (MSA) but with much lower computational complexity. Besides, the decoder achieves high hardware utilization with real-time processing capability. Synthesized with UMC 90nm process, the decoder chip area, throughput and average power dissipation are 1.42M gates, 16Gbps and 368mW, respectively, at 500MHz clock rate. Compared with existing BP-based designs, it has much smaller chip area and lower power dissipation, with comparable performances.
A systematic optimized comparison algorithm for fast LDPC decoding
(2007)
Hung, Jui-Hui
;
Chen, Sau-Gee
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper proposes a novel systematic optimization algorithm for comparison operations required by a check node unit (CNU) in LDPC decoding, given any input number N-in. The algorithm can automatically synthesize an optimized fast comparison operations that guarantees a shortest comparison delay time of [log(2) (N-in - 1)] T-cmp and a minimized total number of two-input comparators, where T-cmp is the delay time of a comparator. High speed is achieved by adopting parallel divide-and-conquer comparison operations, while the required comparators are minimized by developing a novel set construction algorithm that maximizes shareable comparison operations. The designed CNU is favourable to the existing CNU designs which are non-systematically designed with either longer critical path delays or higher comparator counts than the proposed designs. The proposed design is particularly good for long code length cases, when it is impractical to do customized optimized designs by hand, due to high design complexity.
A systematic optimized comparison algorithm for LDPC decoder
(2008)
Hung, Jui-Hui
;
Hung, Jui-Hung
;
Chen, Sau-Gee
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper proposes a novel systematic optimized comparison algorithm for LDPC codes with arbitrary code lengths. Based on the presented algorithm, we also design a corresponding decoder architecture which has a short comparison delay time of [log(2)(n-1)] and a very low comparator complexity of n x [log(2) (n - 1)], where n is the input number to CNU. Besides, the proposed design is general, systematic and flexible, which can be applied to arbitrary input number of a CNU. The designed CNU is favorable to the existing CNU designs which are non-systematically designed with either longer critical path delays or higher comparator counts than the proposed designs. The proposed design is particularly good for long code length cases, when it is impractical to do customized optimized designs by hand, due to high design complexity.
An Effective Multibit-Flipping Algorithm for LDPC Decoding
(2008)
Hung, Jui-Hui
;
Chen, Sau-Gee
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
For LDPC decoding, bit-flipping (BF) algorithms are much simpler than the min-sum algorithms (MSA). However, BF algorithms have the disadvantages of poorer performances and higher iteration counts than MSA. To increase the BF performances, this paper presents a novel BF algorithm, called Low-Correlation Multibit-flipping (LCMBF) algorithm, which flips more than one bit in each iteration. High performances are achieved by flipping those bits with low correlation as much as possible. As such, the chances of introducing additional error bits are greatly reduced. Overall, the proposed algorithm achieves better BER performances and requires less iteration numbers than conventional BF algorithms.
An Efficient BF LDPC Decoding Algorithm Based on A Syndrome Vote Scheme
(2008)
Hung, Jui-Hui
;
Chen, Sau-Gee
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work presents a high-performance bit-flipping (BF) algorithm utilizing a proposed syndrome vote technique of a defined culprit bit set, named CVBF algorithm for LDPC decoding. It can achieve significant decoding performance improvements by about 0.9dB over the most efficient BF algorithm, owing to the introduced an additional syndrome vote procedure after updating the flipping reliabilities of all the received bits in each iteration. Moreover, its performance is comparable to the min-sum algorithm (MSA) under the condition of same iteration number, but with much lower complexity per iteration. The proposed syndrome vote scheme only costs little overhead in hardware realization. Besides, an early termination strategy suited for the proposed algorithm is also devised to further reduce the iteration number.
An Efficient LDPC Decoder Architecture with a High-Performance Decoding Algorithm
(2010-11-01)
Hung, Jui-Hui
;
Chen, Sau-Gee
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this work a high performance LDPC decoder architecture is presented It is a partially parallel architecture for low complexity consideration In order to eliminate the idling time and hardware complexity in conventional partially parallel decoders the decoding process decoder architecture and memory structure are optimized Particularly the parity check matrix is optimally partitioned into four unequal sub matrices that lead to high efficiency in hardware sharing As a result it can handle two different codewords simultaneously with 100% hard ware utilization Furthermore for minimizing the performance loss due to round off errors in fixed point implementations the well known mod died min sum decoding algorithm is enhanced by our recently proposed high performance CMVP decoding algorithm Overall the proposed de coder has high throughput low complexity and good BER performances In the circuit implementation example of the (576 288) parity check matrix for IEEE 802 16e standard the decoder achieves a data rate of 5 5 Gbps assuming 10 decoding iterations and 7 quantization bits with a small area of 653K gates based on UMC 90 nm process technology
An Efficient LDPC Decoder Architecture with a High-Performance Decoding Algorithm
(2010-11-01)
Hung, Jui-Hui
;
Chen, Sau-Gee
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this work a high performance LDPC decoder architecture is presented It is a partially parallel architecture for low complexity consideration In order to eliminate the idling time and hardware complexity in conventional partially parallel decoders the decoding process decoder architecture and memory structure are optimized Particularly the parity check matrix is optimally partitioned into four unequal sub matrices that lead to high efficiency in hardware sharing As a result it can handle two different codewords simultaneously with 100% hard ware utilization Furthermore for minimizing the performance loss due to round off errors in fixed point implementations the well known mod died min sum decoding algorithm is enhanced by our recently proposed high performance CMVP decoding algorithm Overall the proposed de coder has high throughput low complexity and good BER performances In the circuit implementation example of the (576 288) parity check matrix for IEEE 802 16e standard the decoder achieves a data rate of 5 5 Gbps assuming 10 decoding iterations and 7 quantization bits with a small area of 653K gates based on UMC 90 nm process technology