Browsing by Author "Hung, Min-Feng"

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A 2-bit/Cell Gate-All-Around Flash Memory of Self-Assembled Silicon Nanocrystals
(2013-02-01)
Chen, Hung-Bin
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Chang, Chun-Yen
;
Hung, Min-Feng
;
Tang, Zih-Yun
;
Cheng, Ya-Chi
This work presents gate-all-around (GAA) polycrystalline silicon (poly-Si) nanowires (NWs) channel poly-Si/SiO2/Si3N4/SiO2/poly-Si (SONOS) nonvolatile memory (NVM) with a self-assembled Si nanocrystal (Si-NC) embedded charge trapping (CT) layer. Fabrication of the Si-NCs is simple and compatible with the current flash process. The 2-bit operations based on channel hot electrons injection for programming and channel hot holes injection for erasing are clearly achieved by the localized discrete trap. In the programming and erasing characteristics studies, the GAA structure can effectively reduce operation voltage and shorten pulse time. One-bit programming or erasing does not affect the other bit. In the high-temperature retention characteristics studies, the cell embedded with Si-NCs shows excellent electrons confinement vertically and laterally. With respect to endurance characteristics, the memory window does not undergo closure after 10(4) program/erase (P/E) cycle stress. The 2-bit operation for GAA Si-NCs NVM provides scalability, reliability and flexibility in three-dimensional (3D) high-density flash memory applications. (C) 2013 The Japan Society of Applied Physics
Comprehensive Study of Pi-Gate Nanowires Poly-Si TFT Nonvolatile Memory With an HfO(2) Charge Trapping Layer
(2011-03-01)
Chen, Lun-Jyun
;
Wu, Yung-Chun
;
Chiang, Ji-Hong
;
Hung, Min-Feng
;
Chang, Chin-Wei
This work demonstrates the feasibility of a polycrystalline silicon thin-film transistor (poly-Si TFTs) nonvolatile memory (NVM) that utilizes a Pi-shaped gate (Pi-gate) and multiple nanowire channels with a HfO(2) charge-trapping layer. The TFT NVM with the Pi-gate nanowires (NWs) structure has a higher program/erase (P/E) efficiency than that of the conventional single-channel TFT NVM; the memory window can achieve 2.3 V, only needs a programming time of 1 mu s. This high P/E efficiency follows from the improved gate control of the Pi-gate structure. A Pigate NWs poly-Si TFT NVM with a Si(3)N(4) charge-trapping layer was also fabricated. Since HfO(2) has a deeper conduction band than Si(3)N(4), the device with the HfO(2) charge-trapping layer has a higher programming efficiency and the better retention characteristics than that with the Si(3)N(4) charge-trapping layer. Additionally, the high programming efficiency allows the device with the HfO(2) charge-trapping layer to undergo more P/E cycles than that with the Si(3)N(4) charge-trapping layer.
Comprehensive Study of Pi-Gate Nanowires Poly-Si TFT Nonvolatile Memory With an HfO2 Charge Trapping Layer
(2011-03-01)
Chen, Lun-Jyun
;
Wu, Yung-Chun
;
Chiang, Ji-Hong
;
Hung, Min-Feng
;
Chang, Chin-Wei
This work demonstrates the feasibility of a polycrystalline silicon thin-film transistor (poly-Si TFTs) nonvolatile memory (NVM) that utilizes a Pi-shaped gate (Pi-gate) and multiple nanowire channels with a HfO2 charge-trapping layer. The TFT NVM with the Pi-gate nanowires (NWs) structure has a higher program/erase (P/E) efficiency than that of the conventional single-channel TFT NVM; the memory window can achieve 2.3 V, only needs a programming time of 1 mu s. This high P/E efficiency follows from the improved gate control of the Pi-gate structure. A Pigate NWs poly-Si TFT NVM with a Si3N4 charge-trapping layer was also fabricated. Since HfO2 has a deeper conduction band than Si3N4, the device with the HfO2 charge-trapping layer has a higher programming efficiency and the better retention characteristics than that with the Si3N4 charge-trapping layer. Additionally, the high programming efficiency allows the device with the HfO2 charge-trapping layer to undergo more P/E cycles than that with the Si3N4 charge-trapping layer.
Fabrication, characterization and simulation of Omega-gate twin poly-Si FinFET nonvolatile memory
(2013-07-22)
Yeh, Mu-Shih
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Wu, Yung-Chun
;
Hung, Min-Feng
;
Liu, Kuan-Cheng
;
Jhan, Yi-Ruei
This study proposed the twin poly-Si fin field-effect transistor (FinFET) nonvolatile memory with a structure that is composed of Omega-gate nanowires (NWs). Experimental results show that the NW device has superior memory characteristics because its Omega-gate structure provides a large memory window and high program/erase efficiency. With respect to endurance and retention, the memory window can be maintained at 3.5 V after 10(4) program and erase cycles, and after 10 years, the charge is 47.7% of its initial value. This investigation explores its feasibility in the future active matrix liquid crystal display system-on-panel and three-dimensional stacked flash memory applications.
Poly-Si Nanowire Nonvolatile Memory With Nanocrystal Indium-Gallium-Zinc-Oxide Charge-Trapping Layer
(2010-12-01)
Chen, Lun-Chun
;
Wu, Yung-Chun
;
Lin, Tien-Chun
;
Huang, Jyun-Yang
;
Hung, Min-Feng
This letter introduces a polycrystalline silicon (poly-Si) thin-film nonvolatile memory (NVM) with a nanocrystal (NC) indium-gallium-zinc-oxide (IGZO) charge-trapping layer. Experimental results indicate that this NVM exhibits high and symmetric program/erase speeds through the Fowler-Nordheim tunneling mechanism. The memory window loss of the NVM with NC IGZO charge-trapping layer is 25% after 10(4) s at 85 degrees C due to deep quantum well, as well as high-density and deep trap sites in NC IGZO charge-trapping layer. Accordingly, a poly-Si thin-film transistor with NC IGZO charge-trapping layer is promising for NVM applications.