Browsing by Author "Hung, Shao-Feng"

Now showing 1 - 8 of 8

A Cost-Effective Angle Demodulator IC for Path Matched Differential Interferometry Based Sensors
(2014)
Hong, Hao-Chiao
;
Chen, Yun-Tse
;
Hung, Shao-Feng
;
Wu, Chin-Cheng
;
Chiu, Yi
The angle demodulator (ADM) is a key component for the path matched differential interferometry (PMDI) sensors. Conventional ADMs require tens of operational amplifiers (OPAMPs) and bulky capacitors and resistors, making them diflicult to be realized as integrated circuits (ICs). This paper presents the first ADM IC design that requires only one OPAMP and thus saves significant area and power. In addition, this novel ADM design tolerates a wide range of modulation depth of the optical interferometer of the PMDI sensors. As a result, the yield of the PMDI sensor significantly increases. A test chip has been designed and successfully verified in 0.18-mu m CMOS. The active area of the proposed circuits is only 476 by 368 mu m(2) and it consumes only 6.26 mW.
A Cost-Effective Stimulus Generator for Battery Channel Characterization in Electric Vehicles
(2014)
Hung, Shao-Feng
;
Lin, Long-Yi
;
Hong, Hao-Chiao
;
電機學院
;
College of Electrical and Computer Engineering
The battery management system (BMS) is substantial in diagnosing and controlling the battery modules of emerging electric vehicles (EVs). This paper presents a cost-effective stimulus generator for characterizing the communication channels between the BMS host controller and the battery cells. The characterization data are useful to enhance the reliability of the communication. The proposed stimulus generator only consists of a digital oscillator, a reconfigurable digital Sigma-Delta modulator, and an output driver. The all-digital design saves the power and the hardware cost. The digital oscillator provides digital sine waves with well-controlled frequency and amplitude. The proposed reconfigurable digital Sigma-Delta modulator allows generating pulse-density-modulated (PDM) bit-streams of particular frequencies that cover the whole band of interest. Hence, the test accuracy is no less than that of conventional sinusoidal waves. Simulation results show that the generated stimuli have very high narrow-band SNRs that is essential to test the frequency responses of the channels.
A Fully Integrated BIST Delta Sigma ADC Using the In-Phase and Quadrature Waves Fitting Procedure
(2014-12-01)
Hung, Shao-Feng
;
Hong, Hao-Chiao
;
電機資訊學士班
;
Undergraduate Honors Program of Electrical Engineering and Computer Science
This paper demonstrates a fully integrated builtin self-test (BIST) Delta Sigma analog-to-digital converter (ADC) based on the proposed in-phase and quadrature waves fitting (IQWF) procedure. The IQWF procedure enables accurately measuring the phases and amplitudes of test responses so as to enhance the test accuracy of the BIST circuitry. The all-digital BIST circuitry, with on-chip stimulus generator and response analyzer, conducts single-tone functional tests to test for the ADCs characterization results such as signal-to-noise-and-distortion ratio (SNDR), dynamic range (DR), frequency response, input-referred offset, and gain error. Since the IQWF procedure is performed successively in real time, the BIST circuitry does not need huge memory to store all the output samples like conventional fast Fourier transform (FFT) analysis does. The overall hardware overhead only consists of 16.6 k digital gates. The fully integrated BIST Delta Sigma ADC has been fabricated in 0.18-mu m CMOS. Measurement results show that the BIST circuitry reports a peak SNDR of 88.0 dB and a DR of 92.6 dB while the corresponding FFT-based analog tests result in 88.8 and 94.1 dB, respectively. Particularly, the BIST circuitry achieves a test bandwidth as wide as the ADCs 20-kHz rated bandwidth, which is the widest to the best of our knowledge. The proposed BIST ADC can be tested without costly external test resources and is thus well suited for the applications in which conventional test resources are not available such as 3-D ICs.
A Fully Integrated Built-In Self-Test Sigma-Delta ADC Based on the Modified Controlled Sine-Wave Fitting Procedure
(2010-09-10)
Hong, Hao-Chiao
;
Su, Fang-Yi
;
Hung, Shao-Feng
;
電機工程學系
;
Department of Electrical and Computer Engineering
This paper demonstrates the first fully integrated built-in self-test (BIST) Sigma-Delta analog-to-digital converter (ADC) chip to the best of our knowledge. The ADC under test (AUT) comprises a second-order design-for-digital-testability Sigma-Delta modulator and a decimation filter. The purely digital BIST circuitry conducts single-tone tests for the signal-to-noise-and-distortion ratio (SNDR), the dynamic range, the offset, and the gain error of the AUT. The BIST design is based on the proposed modified controlled sine-wave fitting procedure to address the component overload issues, reduce the setup parameter numbers, and eliminate the need for parallel multipliers. The total gate count of the whole BIST circuitry is only 13 300. The hardware overhead is much less than the BIST design using the traditional fast Fourier transform (FFT) analysis. Measurement results show that the peak SNDR results of the proposed BIST design and the conventional FFT analysis are 75.5 and 75.3 dB, respectively. The subtle SNDR difference is already within analog test uncertainty. The BIST Sigma-Delta ADC achieves a digital test bandwidth higher than 17 kHz, very close to the rated 20-kHz bandwidth of the AUT.
A Low-Cost Output Response Analyzer for the Built-in-Self-Test Sigma-Delta Modulator Based on the Controlled Sine Wave Fitting Method
(2009)
Hung, Shao-Feng
;
Hong, Hao-Chiao
;
Liang, Sheng-Chuan
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper proposes I low-cost output response analyzer (ORA) for the built-in-self-test (BIST) Sigma-Delta ADC based on the controlled sine wave fitting (CSWF) method. The ADC under test (AUT) is composed of a design-for-digital-testability (DfDT) second-order E-A modulator and a decimation filter. The CSWF BIST procedure requests in ORA to accept the output of the AUT and calculates the offset, the amplitude of the stimulus tone response, and the total-harmonic-distortion-and-noise (THD+N) power in three successive BIST steps respectively. Each BIST step needs all accumulator to conduct the specified BIST function. By sharing an accumulator for every BIST step, the proposed ORA design contains only 1.9k gates without loss of computational accuracy. The hardware is only 34% of the original design. Simulation results show that the proposed ORA presents accurate SNDR results for the 1 kHz tests.
An Angle Demodulator IC Using Periodically Reset Integration for Path Matched Differential Interferometry-Based Sensors
(2016-06-15)
Hong, Hao-Chiao
;
Chen, Yun-Tse
;
Hung, Shao-Feng
;
Wu, Chin-Cheng
;
Chiu, Yi
The angle demodulator (ADM) is a key component for sensors based on angle modulation such as in the path matched differential interferometry (PMDI). Conventional ADMs require tens of operational amplifiers (OPAMPs) and bulky capacitors and resistors, making them difficult to be realized as integrated circuits (ICs). Furthermore, the state-of-the-art ADMs demand precisely controlled modulation indices. Thus, the practical optical modulators in the interferometers cannot but need sophisticated and costly calibrations to precisely control the modulation indices. This paper presents the first ADM IC designed for the PMDI-based sensors. It requires only one OPAMP and thus saves significant area and power, making it best suitable for portable applications. In addition, this novel ADM design tolerates a wide range of the modulation depth of the optical interferometer. As a result, the yield of the PMDI sensor significantly increases and no calibration for an accurate modulation index is necessary. A test chip of the proposed ADM has been designed and successfully verified in 0.18-mu m CMOS. The active area of the proposed circuits is only 476 x 368 mu m(2) and it consumes only 6.26 mW.
Experimental Results of Testing a BIST epsilon-Delta ADC on the HOY Wireless Test Platform
(2012-10-01)
Hung, Shao-Feng
;
Hong, Hao-Chiao
;
電機資訊學士班
;
電控工程研究所
;
Undergraduate Honors Program of Electrical Engineering and Computer Science
High pin count packaging and 3D IC technology make testing such advanced ICs more and more difficult and expensive. The HOY wireless test platform provides an alternative and cost-effective test solution to address the poor accessibility and high test cost issues. The key idea is implementing a low-cost and short-distance wireless transceiver on chip so that all test instructions and data can be transmitted without physical access. Due to the limited wireless bandwidth, all modules in the device under test (DUT) are preferred to have some built-in self-test (BIST) features. Prior works successfully demonstrated that DUTs with memory and digital circuits can be tested on the low-cost wireless test platform. However, there is no example to show if it is also possible to test the DUT embedded with analog circuits on the HOY test platform. This paper demonstrates the first system-level integration including hardware and software for testing a fully-integrated BIST ADC on the HOY wireless test platform. The DUT chip fabricated in 0.18-mu m CMOS consists of a second-order I -I" pound ADC under test (AUT) and the BIST circuitry. The AUT design employs the decorrelating design-for-digital-testability ((DT)-T-3) scheme to make itself digitally testable. The BIST design is based on the modified controlled sine wave fitting (CSWF) method. The required BIST circuits are purely digital and as small as 9.9k gates. The gate count of the HOY test wrapper is less than 1k. Experimental results obtained by the HOY wireless test platform show that the AUT achieves a dynamic range of 85.1 dB and a peak SNDR of 78.6 dB. The wireless test results show good agreement with those acquired by conventional analog tests.
Testing the Fleischer-Laker Switched-Capacitor Biquad Using the Diagnosis-After-Test Procedure
(2012)
Hung, Shao-Feng
;
Lin, Long-Yi
;
Hong, Hao-Chiao
;
電機工程學系
;
Department of Electrical and Computer Engineering
This paper demonstrates an efficient diagnosis-after-test (DAT) procedure for testing the Fleischer-Laker SC biquad based on the static linear behavior (SLB) analog fault model. For typical switched-capacitor (SC) filter design, the transfer functions are mainly determined by capacitor ratios. Therefore, the practical capacitor ratios are important parameters for designers to diagnose their designs. The DAT procedure can not only test for the real transfer function of the SC biquad for making reliable pass/fail decision without conducting many tests, but also diagnose the capacitor ratios of the SC biquad. With the diagnosis results, designers can find out which capacitors cause the failure and revise the design for a better yield. Mathematical analysis shows that the entire DAT procedure requires only a three-tone test, which implies a very short test time. A second-order low-pass filter adopting the E-circuit of the Fleischer-Laker SC biquad is taken as a test example. Simulation results show the DAT procedure can provide good test accuracy with the three-tone test data. In addition, the test achieves a 100% parametric fault coverage of the capacitor ratios defined by the SLB fault model for the Fleischer-Laker SC biquad.