Browsing by Author "Hung, Sheng-Chin"

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Circuit-Simulation-Based Multi-Objective Evolutionary Algorithm for Design Optimization of a-Si:H TFTs Gate Driver Circuits Under Multilevel Clock Driving
(2015-08-01)
Hung, Sheng-Chin
;
Chiang, Chien-Hsueh
;
Li, Yiming
;
傳播研究所
;
電機資訊學士班
This work optimizes dynamic characteristic of a new amorphous silicon gate (ASG) driver circuit using multi-objective evolutionary algorithm (MOEA) and hydrogenated amorphous silicon (a-Si:H) TFT circuit simulator running on the platform of unified optimization framework (UOF). The ASG driver circuit consisting of 17 a-Si:H TFTs is optimized for the given specifications of the fall time <3 mu s and the ripple voltage < - 9 V while simultaneously minimizing the total layout area. More than 50% reductions on the fall time of the ASG driver circuit have been achieved by using the optimization methodology together with a novel three-level clock driving technique. The measured results of the fabricated sample using the optimized parameters confirm the practicability of reported MOEA methodology.
Circuit-Simulation-Based Multi-objective Evolutionary Algorithm with Multi-Level Clock Driving Technique for a-Si:H TFTs Gate Driver Circuit Design Optimization
(2015-01-01)
Hung, Sheng-Chin
;
Chen, Chieh-Yang
;
Chiang, Chien-Hsueh
;
Li, Yiming
;
分子醫學與生物工程研究所
In this work, dynamic characteristic of a new amorphous silicon gate (ASG) driver circuit is optimized by using multi-objective evolutionary algorithm (MOEA) and hydrogenated amorphous silicon (a-Si:H) TFT circuit simulator on the unified optimization framework (UOF). The ASG driver circuit consisting of 14 a-Si:H TFTs is optimized for the given specifications of the fall time < 3 mu s and the ripple voltage < -9 V with simultaneously minimizing the total layout area. More than 50% reductions on the falling time of the ASG driver circuit have been achieved by using the proposed optimization methodology together with a novel 3-level clock driving technique.