Browsing by Author "Hung, Tao-Yi"

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ESD Protection Design of High-Linearity SPDT CMOS T/R Switch for Cellular Applications
(2019-01-01)
Hung, Tao-Yi
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Electrostatic discharge (ESD) protection design for high-linearity single-pole double-throw (SPDT) transmit/receive switch (T/R switch) at 0.9/1.8 GHz GSM band was proposed and verified in a standard 0.18-mu m CMOS process. The SPDT CMOS T/R switch was implemented with body-floating technique, multi-stacked structure, and series-shunt topology to obtain low insertion loss, high power handling capability, and good isolation. With the proposed ESD protection design, the T/R switch can sustain human-body-model (HBM) ESD voltages of 3.5 kV under the posith e-to-V-ss stress and 5 kV under the negative-to-V-ss stress. Experimental results including ESD characteristics, RF performance, and failure analysis are presented.
ESD Protection Design on T/R Switch with Embedded SCR in CMOS Process
(2017-01-01)
Hung, Tao-Yi
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
ESD protection design for the RF transmit/receive switch (T/R switch) with embedded silicon-controlled rectifier (SCR) is proposed, where the SCR device is embedded in the ESD diode and the transistors of T/R switch by layout skill. Silicon chip verified in a 90-nm CMOS process has been measured by TLP and HBM ESD test to confirm its efficiency for ESD protection. The parasitic capacitance from the ESD devices was also measured. Failure analysis by SEM was performed to find the burned-out site on the T/R switch with the proposed design. From the failure analysis SEM pictures, the embedded SCR in the proposed design is actually triggered on to discharge ESD current.
Evaluation of Electrical Performance of Various Tunnel TFETs
(2015)
Huang, Chi
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Hung, Tao-Yi
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Wang, Pei-Yu
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Tsui, Bing-Yue
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電子工程學系及電子研究所
Tunnel field-effect transistor (TFET) is a promising device which has extraordinary performance on subthreshold swing and is feasible for ultralow power applications. However, one of the main factors of power dissipation and circuit delay among different designs of TFET, namely, parasitic capacitances, has not been discussed in detail. In this paper, parasitic capacitance of various types of TFETs are simulate and analyze.