Browsing by Author "Huy-Binh Do"

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HfO2/AIN/ln(0.53)Ga(0.47)As MOS Devices Electrical Properties and Reliability Studies
(2016-01-01)
Yi-Chang, Edward
;
Quang-Ho Luc
;
Huy-Binh Do
;
Chang, Po-Chun
;
Lin, Yueh-Chin
In this article, we demonstrate plasma-enhanced atomic layer deposition (PEALD) as an effective passivation technique to establish high interfacial quality of high-kllnGaAs structures. Performing PEALD-AlN as an interfacial passivation layer (IPL), excellent capacitance-voltage (C-V) characteristics have been achieved for the HfO2/n, p-In0.53Ga0.47As MOSCAPs. The effects of AlN-IPL on the effective work function (EWF) of metal and band alignment of the HfO2/AlN/In0.53Ga0.47As structure have also been investigated. In addition, the multilayer TiNi alloys were applied as gate dielectric for a suitable metal EWF with a small work function variation (WFV). A sub-nm equivalent oxide thickness (EOT) HfO2/AlN/In0.53Ga0.47As MOS device with low density of interface states and low leakage current density was obtained utilizing AlN-IPL and post remote-plasma (PRP) gas as pre- and post-gate treatments in an in-situ ALD process. The device performance and reliability of HfO2/AlN/In0.53Ga0.47As nMOSFETs with in-situ PEALD treatments have also been characterized.
Performance Improvement of InGaAs FinFET Using NH3 Treatment
(2017-01-01)
Chang, Edward Yi
;
Quang-Ho Luc
;
Huy-Binh Do
;
Lin, Yueh-Chin
;
材料科學與工程學系
A marked improvement in the performance and reliability of In0.53Ga0.47As FinFETs have been demonstrated by applying an in situ remote-plasma gas (PRP) treatment. Under nitrogen passivation effects, an excellent immunity to short channel effects (SCEs) is shown for the scaled In0.53Ga0.47As FinFETs. The positive bias temperature instability (PBTI) measurements indicate that the NH3 plasma-treated In0.53Ga0.47As FinFETs are quite reliable with a small threshold voltage shift and a long-term operation. These results suggest that the in situ PRP treatment could be a key process for high-k dielectric technology for the sub-nanometer III-V MOS related devices.