Browsing by Author "Hwang, Jiunn-Ren"

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Characteristic fluctuation dependence on discrete dopant for 16nm SOI FinFETs at different temperature
(2007)
Li, Yiming
;
Hwang, Chih-Hong
;
Yu, Shao-Ming
;
Huang, Hsuan-Ming
;
Yeh, Ta-Ching
In this paper, we numerically study the discrete-dopant-induced characteristic fluctuations in 16nnn silicon-on-insulator (SOI) FinFETs. For devices under different temperature condition, discrete dopants are statistically generated and positioned into the three-dimensional channel region to examine associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". Electrical characteristics' fluctuations are growing worse when the substrate temperature increases, the standard deviation of threshold voltage increases 1.75 times when substrate temperature increases from 300K to 400K for example. This "atomistic" device simulation technique is computationally cost-effective and provides us an insight into the problem of discrete-dopant-induced fluctuation and the relation between the fluctuation and thermal effect.
Discrete dopant fluctuated 20nm/15nm-gate planar CMOS
(2007)
Yang, Fu-Liang
;
Hwang, Jiunn-Ren
;
Chen, Hung-Ming
;
Shen, Jeng-Jung
;
Yu, Shao-Ming
We have, for the first time, experimentally quantified random dopant distribution (RDD) induced V-t standard deviation up to 40mV for 20nm-gate planar CMOS. Discrete dopants have been statistically positioned in the 3D channel region to examine associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". As gate length further scaling down to 15nm, the newly developed discrete-dopant scheme features an effective solution to suppress 3-sigma-edge single digit dopants induced V-t variation by gate work function modulation. The extensive study may postpone the scaling limit projected for planar CMOS.
Discrete dopant fluctuations in 20-nm/15-nm-gate planar CMOS
(2008-06-01)
Li, Yiming
;
Yu, Shao-Ming
;
Hwang, Jiunn-Ren
;
Yang, Fu-Liang
;
資訊工程學系
We experimentally quantified, for the first time, the random dopant distribution (RDD)-induced threshold voltage (V-t) standard deviation up to 40 mV for 20-nm-gate planar complementary metal-oxide-semiconductor (CMOS) field-effect transistors. Discrete dopants have been statistically positioned in the 3-D channel region to examine the associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation." As the gate length further scales down to 15 nm, the newly developed discrete dopant scheme features an effective solution to suppress the 3-sigma-edge single-digit dopant-induced V-t variation by the gate work function modulation. The results of this paper may postpone the scaling limit projected for planar CMOS.
Electrical characteristic fluctuations in sub-45nm CMOS devices
(2006)
Yang, Fu-Liang
;
Hwang, Jiunn-Ren
;
Li, Yiming
;
電信工程研究所
;
Institute of Communications Engineering
Random fluctuations of electrical characteristics in sub-45nm CMOS devices introduced by process-parameter variations through severe short channel effects have made the scaling of conventional planar transistors much more difficult than ever before, especially while further reduction of gate dielectric thickness is ambiguous. In this paper, we systematically investigate the fluctuations of threshold voltages at varied gate length, considering the effects of channel doping, gate dielectric thickness, and new transistor structures such as thin-buried-oxide SOI and FinFETs. Quantitative analysis is undertaken in terms of three major variation sources: random doping distribution, gate length deviation, and line edge roughness. The analysis also features a low V-t-fluctuation transistor for 16nm node achieved with undoped body, mid-gap metal gate, and nanowire channel.
Novel strained CMOS devices with STI stress buffer layers
(2007)
Chen, Hung-Ming
;
Hwang, Jiunn-Ren
;
Li, Yiming
;
Yang, Fu-Liang
;
電信工程研究所
STI stress buffer techniques including sidewall stress buffer and channel surface buffer layers are developed to reduce the impact of compressive STI stress on the mobility of advanced N-MOS devices. For L-g down to 35nm, 7% improvement of drive current at N-MOS has been achieved, while no degradation at P-MOS drive current and maintaining the same junction leakage at both N-MOS and P-MOS. A stress relaxation model with simulation is proposed to account for the enhanced transportation characteristics.
Strained CMOS devices with shallow-trench-isolation stress buffer layers
(2008-04-01)
Li, Yiming
;
Chen, Hung-Ming
;
Yu, Shao-Ming
;
Hwang, Jiunn-Ren
;
Yang, Fu-Liang
In this brief, shallow-trench-isolation (STI) stress buffer techniques, including sidewall stress buffer and channel surface buffer layers, are developed to reduce the impact of compressive STI stress on the mobility of advanced n-type MOS (NMOS) devices. Our investigation shows that a 7% driving current gain at an NMOS device has been achieved, whereas no degradation at a p-type MOS (PMOS) device was observed. The same junction leakage at both the NMOS and PMOS devices was maintained. A stress relaxation model with simulation is thus proposed to account for the enhanced transport characteristics.